M30280F6HP RENESAS [Renesas Technology Corp], M30280F6HP Datasheet - Page 58

• Manufacturer Part Number: M30280F6HP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

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R
M
e
E
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Table 5.2 Low Voltage Detection Interrupt Request Generation Conditions
J
Table 5.3 Sampling Clock Periods
6
NOTES:
0
5.5.1 Low Voltage Detection Interrupt
Operation Mode
CPU
clock
(MHz)
C
2
9
16
If the D40 bit in the D4INT register is set to "1" (low voltge detection interrupt enabled), a low voltage
detection interrupt request is generated when voltage applied to the V
The low voltage detection interrupt shares the same interrupt vector with watchdog timer interrupt and
oscillation stop, re-oscillation detection interrupt.
Set the D41 bit in the D4INT register to "1" (enabled) to use the low voltage detection interrupt to exit stop
mode, set the D41 bit in the D4INT register to 1 (enable).
The D42 bit in the D4INT register is set to "1" (above or below Vdet4 detected) as soon as voltage applied
to the V
"0" to "1", a low voltage detection interrupt is generated. Set the D42 bit to 0 (not detected) by program.
However, when the D41 bit is set to 1 and the microcomputer is in stop mode, a low voltage detection
interrupt request is generated, regardless of the D42 bit setting, if voltage applies to the V
detected to rise above or drop below Vdet4. The microcomputer then exits stop mode.
Table 5.2 shows how a low voltage detection interrupt request is generated.
Bits DF1 and DF0 in the D4INT register determine sampling period that detects voltage applied to the
V
0 .
Wait mode
2 /
Stop mode
1. The status except the wait mode and stop mode is handled as the normal mode. (Refer to 7. Clock generating circuit)
2. Refer to 5.5.2 Limitations on stop mode and 5.5.3 Limitations on wait mode.
3. An interrupt request for voltage reduction is generated a sampling time after the value of the VC13 bit has changed.
B
operation
mode(1)
CC
0
0
Normal
8
Refer to the Figure 5.9 for details.
0
(2)
(2)
4
G
J
pin rises above or drops below Vdet4. Table 5.3 shows sampling periods.
7
a
o r
0 -
. n
(CPU clock divided by 8)
CC
u
2
3
0
p
DF1 to DF0=00
, 1
0
pin goes above or below Vdet4 due to the voltage change. When the D42 bit setting changes
(
M
2
0
3.0
1
0
6
VC27 bit
7
C
2 /
1
, 8
page 38
M
1
6
(CPU clock divided by 16)
C
f o
2 /
D40 bit
DF1 to DF0=01
8
3
1
) B
8
5
6.0
Sampling clock (µs)
D41 bit
1
(CPU clock divided by 32)
DF1 to DF0=10
12.0
D42 bit
0 to 1
0 to 1
(CPU clock divided by 64)
CM02 bit
DF1 to DF0=11
0
1
0
CC
24.0
pin is above or below Vdet4.
0 to 1
1 to 0
0 to 1
1 to 0
0 to 1
0 to 1
VC13 bit
– : “0”or “1”
(3)
(3)
(3)
(3)
CC
pin is
5. Reset