M30280F6HP RENESAS [Renesas Technology Corp], M30280F6HP Datasheet - Page 377

• Manufacturer Part Number: M30280F6HP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

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Figure 20.3 Procedure for Changing the Interrupt Generate Factor
J
6
0
20.4.5 INT Interrupt
C
2
9
2 /
1. Either an “L” level of at least t
2. If the POL bit in the INT0IC to INT5IC registers or the IFSR7 to IFSR0 bits in the IFSR register are
3. When using the INT
0 .
B
0
0
input to pins INT
changed, the IR bit may inadvertently set to 1 (interrupt requested). Be sure to clear the IR bit to 0
(interrupt not requested) after changing any of those register bits.
debounce filter) before entering stop mode.
8
0
G
4
J
7
a
o r
0 -
. n
______
u
2
3
p
0
, 1
NOTES:
0
(
M
2
IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to
1.The above settings must be executed individually. Do not execute two or more settings
2. Use the I flag for the INTi interrupt (i = 0 to 5).
3. Refer to 20.5.6 Rewrite the Interrupt Control Register for details about the
0
1
0
________
6
simultaneously (using one instruction).
For the interrupts from peripheral functions other than the INTi interrupt, turn off the
peripheral function that is the source of the interrupt in order not to generate an interrupt
request before changing the interrupt generate factor. In this case, if the maskable interrupts
can all be disabled without causing a problem, use the I flag. Otherwise, use the corresponding
ILVL2 to ILVL0 bit for the interrupt whose interrupt generate factor is to be changed.
instructions to use and the notes to be taken for instruction execution.
Change the interrupt generate factor (including a mode change of peripheral function)
7
C
2 /
Use the MOV instruction to clear the IR bit to “0” (interrupt not requested)
0
_______
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be changed
through INT
M
5
1
interrupt for exiting stop mode, set the P17DDR register to “FF
6
C
________
2 /
f o
8
3
) B
8
W
5
5
regardless of the CPU operation clock.
(
INL
) or an “H” level of at least t
Changing the interrupt source
Enable interrupts
Disable interrupts
End of change
(2,3)
(2,3)
W
(
INH
) width is necessary for the signal
(3)
16
” (disable digital
20. Precautions