M30280F6HP RENESAS [Renesas Technology Corp], M30280F6HP Datasheet - Page 234

• Manufacturer Part Number: M30280F6HP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

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Table 14.20 SI/O3 and SI/O4 Specifications
NOTES:
6
0
Interrupt request
generation timing
Transfer data format
Transfer clock
Transmission/reception
start condition
CLKi pin fucntion
S
SINi pin function
Select function
C
2
9
OUT
1. To set the SMi6 bit in the SiC register to “0” (external clock), follow the procedure described below.
2. Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer. Therefore,
3. When the SMi6 bit in the SiC register is set to "1" (internal clock), S
4. When the SMi6 bit in the SiC register is set to "1" (internal clock), the transfer clock stops in the high state if the
0 .
B
2 /
0
0
8
do not write the next transmit data to the SiTRR register during transmission.
clock period after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit
data is written to the SiTRR register during this period, S
the data hold time thereby reduced.
SMi4 bit is set to "0", or stops in the low state if the SMi4 bit is set to "1".
0
i pin function
• If the SMi4 bit in the SiC register is set to "0", write transmit data to the SiTRR register while input on the CLKi
• If the SMi4 bit is set to "1", write transmit data to the SiTRR register while input on the CLKi pin is low. The
• Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop the
4
J
G
pin is high. The same applies when rewriting the SMi7 bit in the SiC register.
same applies when rewriting the SMi7 bit.
transfer clock after supplying eight pulses. If the SMi6 bit is set to "1" (internal clock), the transfer clock
automatically stops.
7
a
o r
0 -
. n
2
u
Item
3
0
p
, 1
0
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2
0
1
0
6
7
C
2 /
page 214
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1
6
• Transfer data length: 8 bits
• The SMi6 bit in the SiC (i=3, 4) register is set to “1” (internal clock) : fj/ (2(n+1))
• SMi6 bit is set to “0” (external clock) : Input from CLKi pin
• Before transmission/reception can start, the following requirements must be met
• When the SMi4 bit in the SiC register is set to "0"
• When SMi4 is set to "1"
I/O port, transfer clock input, transfer clock output
I/O port, transmit data output, high-impedance
I/O port, receive data input
• LSB first or MSB first selection
• Function for setting an S
• CLK polarity selection
C
fj = f
Write transmit data to the SiTRR register
The rising edge of the last transfer clock pulse
The falling edge of the last transfer clock pulse
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
When the SMi6 bit in the SiC register is set to "0" (external clock), the S
output level while not tranmitting can be selected.
Whether transmit data is output/input timing at the rising edge or falling edge of
transfer clock can be selected.
f o
2 /
8
3
1SIO
) B
8
5
, f
2SIO
, f
8SIO
, f
32SIO
OUT
. n=Setting value of SiBRG register
OUTi
i initial value set function
immediately goes to a high-impedance state, with
Specification
OUTi
(2, 3)
retains the last data for a 1/2 transfer
(4)
(4)
(1)
00
16
to FF
OUT
14. Serial I/O
i pin
16
.