M30280F6HP RENESAS [Renesas Technology Corp], M30280F6HP Datasheet - Page 61

• Manufacturer Part Number: M30280F6HP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

R
R
M
6. Processor Mode
e
E
1
. v
Figure 6.1 PM0 Register, PM1 Register
J
6
0
The microcomputer supports single-chip mode only. Figures 6.1 and 6.2 show the associated registers.
C
2
9
0 .
2 /
B
0
0
8
0
Processor Mode Register 0
NOTES:
Processor Mode Register 1
4
G
J
0
b7
b7
NOTES:
7
a
o r
1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
0 -
. n
0
1. Rewrite the PM1 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
2. To access the two 2K-byte data spaces in data block A and data block B, set the PM10 bit to "1". The PM10
3. When the FMR01 bit in the FMR0 register is set to "1" (enables CPU rewrite mode), the PM10 bit is
4. Set the PM12 bit to "1" by program. (Writing "0" by program has no effect)
5. When the PM17 bit is set to "1" (wait state), one wait is inserted when accessing the internal RAM or the
b6
0
b6
u
2
3
p
0
bit is not available in mask version.
automatically set to "1".
internal ROM.
, 1
b5
0 0
0
0 0
b5
(
M
2
b4
0
b4
1
0
6
7
C
b3
b3
1
2 /
0
b2
b2
, 8
page 41
0 0
b1
b1
0
M
1
b0
b0
6
C
f o
2 /
Bit Symbol
Bit Symbol
(b2-b0)
(b7-b4)
(b6-b4)
8
PM03
PM10
PM12
PM17
3
(b1)
(b3)
) B
Symbol
PM0
8
Symbol
PM1
5
(1)
(1)
Reserved bit
Software reset bit
Reserved bit
Flash data block access
bit
Reserved bit
Watchdog timer function
select bit
Reserved bit
Reserved bit
Wait bit
(2)
Address
0004
Bit Name
Bit Name
Address
0005
(5)
16
16
After Reset
00001000
After Reset
00
Set to "0"
Set to "0"
The microcomputer is reset when
this bit is set to "1". When read,
its content is "0".
0: Disabled
1: Enabled
Set to "0"
0 : Watchdog timer interrupt
1 : Watchdog timer reset
Set to "1"
Set to "0"
0 : No wait state
1 : Wait state (1 wait)
16
2
(3)
Function
Function
(4)
6. Processor Mode
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW