M30280F6HP RENESAS [Renesas Technology Corp], M30280F6HP Datasheet - Page 43

• Manufacturer Part Number: M30280F6HP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

R
R
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2.3 Frame Base Register (FB)
2.4 Interrupt Table Register (INTB)
2.5 Program Counter (PC)
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
2.7 Static Base Register (SB)
2.8 Flag Register (FLG)
e
E
1
. v
J
6
0
FB is configured with 16 bits, and is used for FB relative addressing.
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
PC is configured with 20 bits, indicating the address of an instruction to be executed.
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
SB is configured with 16 bits, and is used for SB relative addressing.
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
2.8.2 Debug Flag (D Flag)
2.8.3 Zero Flag (Z Flag)
2.8.4 Sign Flag (S Flag)
2.8.5 Register Bank Select Flag (B Flag)
2.8.6 Overflow Flag (O Flag)
2.8.7 Interrupt Enable Flag (I Flag)
2.8.8 Stack Pointer Select Flag (U Flag)
2.8.9 Processor Interrupt Priority Level (IPL)
2.8.10 Reserved Area
C
2
9
0 .
B
2 /
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag
is cleared to “0” when the interrupt request is accepted.
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level
0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
When write to this bit, write "0". When read, its content is undefined.
0
0
8
0
4
G
J
7
a
o r
0 -
. n
u
2
3
0
p
, 1
0
(
M
2
0
1
0
6
7
C
2 /
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page 23
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2. Central Processing Unit(CPU)