M30280F6HP RENESAS [Renesas Technology Corp], M30280F6HP Datasheet - Page 201

• Manufacturer Part Number: M30280F6HP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

M
R
R
1
e
E
Figure 14.14 Transfer Clock Output From Multiple Pins
. v
6
Figure 14.13 Serial data logic switch timing
J
0
C
2
9
2 /
0 .
B
14.1.1.4 Continuous receive mode
14.1.1.5 Serial data logic switch function (UART2)
14.1.1.6 Transfer clock output from multiple pins function (UART1)
8
0
0
0
When the UiRRM bit (i=0 to 2) is set to "1" (continuous receive mode), the TI bit in the UiC1 register is
set to “0” (data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit
is set to "1", do not write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits
are the bit 2 and bit 3 in the UCON register, respectively, and the U2RRM bit is the bit 5 in the U2C1
register.
When the U2LCH bit in the U2C1 register is set to "1" (reverse), the data written to the U2TB register
has its logic reversed before being transmitted. Similarly, the received data has its logic reversed
when read from the U2RB register. Figure 14.13 shows serial data logic.
The CLKMD1 to CLKMD0 bits in the UCON register can choose one from two transfer clock output
pins. (See Figure 14.14)This function is valid when the internal clock is selected for UART1.
G
4
J
7
a
o r
0 -
. n
u
2
p
3
0
, 1
0
(
M
NOTES:
2
Microcomputer
1
0
0
6
1. This applies to the case where the CKDIR bit in the U1MRregister is set to "0" (internal clock)
2. This applies to the case where U1MAP bit in PACR register is set to “0” (P6
7
C
CLKS
and the CLKMD1 bit in the UCON register is set to "1" (transfer clock output from multiple
pins).
CLK
T
2 /
Transfer clock
Transfer clock
X
NOTES:
(2) When the U2LCH bit in the U2C1 register is set to "1" (reverse)
D
, 8
(1) When the U2LCH bit in the U2C1 register is set to "0" (no reverse)
page 181
1
1
1
(no reverse)
1. This applies to the case where the CKPOL bit in the U2C0 register
(P6
(P6
(P6
M
(reverse)
is set to "0" (transmit data output at the falling edge and the
receive data taken in at the rising edge of the transfer clock) and
the UFORM bit is set to "0" (LSB first).
1
TxD
4
5
7
TxD
)
)
)
6
C
2
2
2 /
“H”
f o
“H”
“H”
“H”
“L”
“L”
“L”
“L”
8
3
) B
8
5
D0
D0
Transfer enabled
when the CLKMD0
bit in the UCON
register is set to "0"
IN
CLK
D1
D1
D2
D2
D3
D3
D4
D4
Transfer enabled
when the CLKMD0
bit in the UCON
register is set to "1"
D5
D5
CLK
IN
D6
D6
D7
D7
7
to P6
4
).
14. Serial I/O