M30280F6HP RENESAS [Renesas Technology Corp], M30280F6HP Datasheet - Page 203

• Manufacturer Part Number: M30280F6HP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

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Table 14.5 UART Mode Specifications
NOTES:
. v
6
J
Interrupt request
generation timing
14.1.2 Clock Asynchronous Serial I/O (UART) Mode
Transfer data format
Transfer clock
Transmission, reception control
Transmission start condition
Reception start condition
Error detection
Select function
0
C
2
9
1. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains unchanged.
2. The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Table 14.5 lists the specifications of the UART mode.
2 /
0 .
B
8
0
0
0
G
4
J
7
a
o r
0 -
. n
u
Item
2
p
3
0
, 1
0
(
M
2
1
0
0
6
7
C
2 /
, 8
page 183
M
1
6
• Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
• The CKDIR bit in the UiMR(i=0 to 2) register is set to "0" (internal clock) : fj/ (16(n+1))
• CKDIR bit is set to “1” (external clock ) : f
• Selectable from CTS function, RTS function or CTS/RTS function disable
• Before transmission can start, the following requirements must be met
_
_
_
• Before reception can start, the following requirements must be met"
_
_
• For transmission, one of the following conditions can be selected
_
_
• For reception
• Overrun error
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit in the the next data
• Framing error
• Parity error
• Error sum flag
• LSB first, MSB first selection
• Serial data logic switch (UART2)
• T
• Separate CTS/RTS pins (UART0)
• UART1 pin remapping selection
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
C
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
This function reverses the polarities of hte T
fj = f
f
UiTB register to the UARTi transmit register (at start of transmission)
data from the UARTi transmit register
This error occurs when the number of stop bits set is not detected
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
This flag is set to "1" when any of the overrun, framing, and parity errors is encountered
logic levels of all I/O data is reversed.
The TE bit in the UiC1 register is set to 1 (transmission enabled)
The TI bit in the UiC1 register is set to "0" (data present in UiTB register)
If CTS function is selected, input on the CTSi pin is set to “L”
The RE bit in the UiC1 register is set to "1" (reception enabled)
Start bit detection
The UiIRS bit
The UiIRS bit is set to"1" (transfer completed): when the serial I/O finished sending
_________
CTS
The UART1 pin can be selected from the P6
EXT
2 /
X
f o
_______
D, R
8
: Input from CLKi pin.
1SIO
3
) B
0
8
and RTS
5
X
D I/O polarity switch (UART2)
, f
_______ _______
2SIO
_________
(2)
(1)
, f
0
8SIO
_______
is set to "0" (transmit buffer empty): when transferring data from the
are input/output from separate pins
, f
32SIO
. n: Setting value of UiBRG register
n :Setting value of UiBRG register
Specification
_______
_______
EXT
X
/16(n+1)
7
D pin output and R
to P6
_______ _______
4
or P7
3
to P7
X
D pin input. The
00
0
00
16
16
to FF
to FF
14. Serial I/O
16
16