M30280F6HP RENESAS [Renesas Technology Corp], M30280F6HP Datasheet - Page 298

• Manufacturer Part Number: M30280F6HP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

R
R
M
e
E
1
. v
J
6
0
16.13.2 Example of Slave Receive
C
2
9
For example, a slave receives data as shown below when following conditions are met: high-speed clock
mode, SCL frequency of 400 kHz, ACK clock added and addressing format.
0 .
B
2 /
0
0
8
0
1) Set a slave address in the 7 high-order bits in the S0D0 register
2) Set "A5
3) Set “00
4) Set “08
5) When a START condition is received, addresses are compared
6) •When the transmitted addresses are all "0" (general call), the ADR0 bit in the S10 register is set to "1"
7) Write dummy data to the S00 register.
8) After receiving 1-byte data, an ACK-CLK bit is automatically returned and an I
9) To determine whether the ACK should be returned depending on contents in the received data, set
10) When receiving more than 1-byte control data, repeat steps 7) and 8) or 7) and 9).
11) When a STOP condition is detected, the communication is ended.
4
J
G
7
a
o r
0 -
•When the transmitted addresses match with the address set in 1), the ASS bit in the S10 register
•In other cases, the ADR0 and AAS bits are set to “0” and I
. n
S3D0 register to generate an ACK clock and set SCL clock frequency at 400kHz (f
interrupt request signal is generated.
dummy data to the S00 register to receive data after setting the WIT bit in te S3D0 register to "1"
(enable the I
interrupt is generated when the 1-byte data is received, set the ACKBIT bit to "1" or "0" to output a
signal from the ACKBIT bit.
and an I
is set to “1” and an I
is not generated.
u
2
3
0
p
, 1
0
(
M
2
0
16
16
16
1
0
2
6
7
" to the S20 register, “000
” to the S10 register to reset transmit/receive mode
” to the S1D0 register to enable data communication
C bus interface interrupt request signal is generated.
C
2 /
page 278
2
, 8
C bus interface interrupt of data receive completion). Because the I
M
1
6
C
2
f o
2 /
C bus interface interrupt request signal is generated.
8
3
) B
8
5
2
” to the ICK4 to ICK2 bits in the S4D0 register, and “00
2
16. MULTI-MASTER I
C bus interface interrupt request signal
2
2
2
C bus INTERFACE
C bus interface
C bus interface
1
=8MHz)
16
” to the