HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 687

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

15.3.3
Figure 15.14 shows output timing when TM is set to 1 in SIFTR.
TDRE
Synchronous internal clock
SITDR
SITSR
STCK
STS
STXD
Note: TM = 1: STS is output
TDRE
Synchronous internal clock
SITDR
SITSR
STCK
STS
STXD
Note: TM = 1: STS is output
Figure 15.13 Transmission: Continuous Transfer Mode (TM = 1 Mode)/LSB First
Figure 15.12 Transmission: Interval Transfer Mode (TM = 1 Mode)/LSB First
DL = 0: 8-bit data transfer
SE = 1: Synchronous transfer in start signal mode
LM = 1: LSB first
TRMD = 0: LSB of transmitted primary data is value in SITDR
DL = 0: 8-bit data transfer
SE = 0: Asynchronous transfer, no start signal mode
LM = 1: LSB first
TRMD = 0: LSB of transmitted primary data is value in SITDR
Output when TRMD = 1 in SIFCR
Set to 1 when the amount of data in SITDR is
less than or equal to the setting of bits
TFWM3 to TFWM0 in SIFCR
Set to 1 when the amount of data in SITDR is
less than or equal to the setting of bits
TFWM3 to TFWM0 in SIFCR
Undefined
Undefined
C[7:0]
C[7:0]
C[0:7]
C[0:7]
C[0]
C[0]
C[1:7]
C[1:7]
D[7:0]
D[7:0]
C[1]
C[1]
C[2:7]
C[2:7]
C[2]
C[2]
Cleared to 0 when an amount of data exceeding
the setting of bits TFWM3 to TFWM0 in SIFCR
has been written to SITDR
Cleared to 0 when an amount of data exceeding
the setting of bits TFWM3 to TFWM0 in SIFCR
has been written to SITDR
Rev. 2.00 Mar 09, 2006 page 661 of 906
Section 15 Serial I/O with FIFO (SIOF)
C[6:7]
D[7:0]
C[7]
D[7:0]
C[6]
C[7]
D[0:7]
C[7]
D[0]
C[7]
D[1:7]
D[0:7]
D[0]
D[1]
REJ09B0292-0200
E[7:0]
D[2:7]
D[1:7]
E[7:0]
D[2]
D[1]
D[2:7]
D[3:7]
D[2]
D[3]