HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 63

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
In addition, among the DSP unit usage registers (DSP registers) described in 2.1.4 DSP Registers,
the DSP status register (DSR) and the five registers A0, X0, X1, Y0 and Y1 of the eight data
registers are treated as system registers. Among these, the A0 is a 40-bit register, but when data is
output from the A0 register, the guard bit section (A0G) is disregarded; when data is input to the
A0 register, the MSB of the data is copied into the guard bit section (A0G).
2.1.4
DSP Registers
The DSP unit has eight data registers and one control register as its DSP registers.
The DSP data registers are comprised of the two 40-bit registers A0 and A1, and the six 32-bit
registers M0, M1, X0, X1, Y0 and Y1. The A0 and A1 registers have the 8-bit guard bits A0G and
A1G, respectively.
The DSP data registers are used for the transfer and processing of the DSP data of DSP instruction
operands. There are three types of instructions that access DSP data registers: those for DSP data
processing, and those for X or Y data transfer processing.
The control register is the 32-bit DSP status register (DSR) that represents operation results. The
DSR register has bits that represent operation results, a signed greater than bit (GT), a zero bit (Z),
a negative value bit (N), an overflow bit (V), a DSP status bit (DC: DSP condition), and a status
selection bit (CS: condition select) for controlling DC bit setting.
The DC bit represents one status flag and is very similar to the SuperH microprocessor CPU core
T bit. For conditional DSP type instructions, DSP data processing execution is controlled in
accordance with the DC bit. This control is related to execution in the DSP unit only, and only
DSP registers are updated. It bears no relation to address calculation or such SuperH
microprocessor CPU core execution instructions as load/store instructions. The control bits CS
(bits 2 to 0) designate the status for setting the DC bit.
DSP type instructions are comprised of unconditional DSP type instructions and conditional DSP
type instructions. The status and DC bits are updated in unconditional DSP type data processing,
with the exception of the PMULS, MOVX, MOVY and MOVS instructions. Conditional DSP
type instructions are executed according to the status of the DC bit, but regardless of whether or
not they are executed, the DSR register is not updated.
Figure 2.4 shows the DSP registers. The DSR register bit functions are shown in table 2.2.
Registers A0, X0, X1, Y0, Y1, and DSR are handled as system registers by CPU core instructions.
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