HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 453

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit 23—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 22—EtherC States Register Interrupt (ECI): Indicates that an interrupt due to an EtherC status
register (ECSR) source has been detected.
Bit 22: ECI
0
1
Note: EESR is a read-only register. When this register is cleared by a source in ECSR in the
Bit 21—Frame Transmit Complete (TC): Indicates that all the data specified by the transmit
descriptor has been transmitted to the EtherC. The transfer status is written back to the relevant
descriptor. When 1-frame transmission is completed for 1-frame/1-buffer processing, or when the
last data in the frame is transmitted and the transmission descriptor valid bit (TACT) in the next
descriptor is not set for multiple-frame buffer processing, transmission is completed and this bit is
set to 1. After frame transmission, the E-DMAC writes the transmission status back to the
descriptor.
Bit 21: TC
0
1
Note: As data is sent onto the line by the PHY-LSI from the EtherC via the MII, the actual
Bit 20—Transmit Descriptor Exhausted (TDE): Indicates that the transmission descriptor valid bit
(TACT) in the descriptor is not set when the E-DMAC reads the transmission descriptor when the
previous descriptor is not the last one of the frame for multiple- buffer frame processing. As a
result, an incomplete frame may be transmitted.
Bit 20: TDE
0
1
Note: When transmission descriptor empty (TDE = 1) occurs, execute a software reset and initiate
transferred to memory when DMA transfer becomes possible. When the frame counter
value falls below 8, another frame is received.
EtherC, this bit is also cleared.
transmission completion time is longer.
transmission. In this case, the address that is stored in the transmit descriptor list address
register (TDLAR) is transmitted first.
EtherC status interrupt source not detected
EtherC status interrupt source detected (interrupt source)
Description
Transfer not complete, or no transfer directive
Transfer complete (interrupt source)
Description
“1” transmit descriptor active bit (TACT) detected
“0” transmit descriptor active bit (TACT) detected (interrupt source)
Description
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 2.00 Mar 09, 2006 page 427 of 906
REJ09B0292-0200
(Initial value)
(Initial value)
(Initial value)