HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 317

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.4.3
Idle cycles can be inserted to prevent extension of the RD or WEn assertion period beyond the
length of the CSn assertion period by setting control bits in WCR3. This allows for flexible
interfacing to external circuit. The timing is shown in figure 7.19. Th and Tf cycles are added
respectively before and after the ordinary cycle. Signals other than RD and WEn are asserted in
this cycle, but RD and WEn are not. In addition, data is extended up to the Tf cycle, which is
effective for devices with slow write operations.
Read
Write
Note: * DACKn waveform when active-low is specified.
CS
CS Assertion Period Extension
CS
CS
RD/WR
DACKn*
CKIO
Address
CSn
BS
RD
Data
WEn
Data
Figure 7.19 CS
CS
CS Assertion Period Extension Function
CS
Th
T1
Rev. 2.00 Mar 09, 2006 page 291 of 906
Section 7 Bus State Controller (BSC)
T2
Tf
REJ09B0292-0200