HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 667

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

15.2.3
SITSR is a 16-bit register used to transmit serial data. The contents of this register are shifted in
MSB-first or LSB-first order, based on the LM bit in SIFCR, in synchronization with the rising
edge of the serial transmit clock (STCK), and output from the serial transmit data STXD pin. The
transfer data length is set by the DL bit in SICTR. The transmit mode bit (TRMD) in SIFCR
controls the LSB of the transmitted primary data or control data.
When the TRMD bit is cleared to 0 and the DL bit is cleared to 0 (8-bit data length), the lower 8
bits in the transmit data register (SITDR) are output. When the DL bit is set to 1 (16-bit data
length), all 16 bits in SITDR are output.
Setting the TRMD bit to 1 causes the LSB of the primary data to be output as 0. Performing write
access to the transmit control data register (SITCDR) in this case, if the DL bit is cleared to 0,
causes the lower 8 bits in SITDR to be output, with the LSB as 1, after which the lower 8 bits in
SITCDR are output. If the DL bit is set to 1, all 16 bits in SITDR are output, with the LSB as 1,
after which all 16 bits in SITCDR are output.
When transmit primary data with a value less than or equal to the transmit FIFO watermark bits
(TFWM3 to TFWM0) in SIFCR is transferred from SITDR to SITSR, the transmit data register
empty flag (TDRE) is set in SISTR. If output of the next primary data begins when the amount of
transmit primary data in SITDR is 0, an underrun error occurs, the transmit underrun error flag
(TERR) in SISTR is set, and an error interrupt request is sent to the INTC.
15.2.4
SITDR is a 16-bit x 16-stage FIFO register that stores primary transmit data. Data should be
written to SITDR when the transmit data register empty flag (TDRE) is set to 1 in SISTR. If data
is written to SITDR when TDRE is 0, a SITDR overflow may occur. When transmit primary data
Initial value:
Initial value:
Transmit Shift Register (SITSR)
Transmit Data Register (SITDR)
R/W:
R/W:
Bit:
Bit:
15
15
—
—
W
0
14
14
—
—
W
0
13
13
—
—
W
0
...
...
...
...
...
...
...
...
Rev. 2.00 Mar 09, 2006 page 641 of 906
Section 15 Serial I/O with FIFO (SIOF)
—
—
W
3
3
0
—
—
W
2
2
0
REJ09B0292-0200
—
—
W
1
1
0
—
—
W
0
0
0