HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 392

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8 Cache
8.4.3
When reading or writing a cache-through area, the cache is not accessed. Instead, the cache
address value is output to the internal address bus. For read operations, the read data output to the
internal data bus is fetched and output to the cache data bus, as shown in figure 8.9. The read of
the cache-through area is only performed on the address in question. For write operations, the
write data on the cache data bus is output to the internal data bus. Writes on the cache through area
are compared to the address tag; except for the fact that nothing is written to the data array, the
operation is the same as the write shown in figure 8.5.
8.4.4
The TAS instruction reads data from memory, compares it to 0, reflects the result in the T bit of
the status register (SR), and sets the most significant bit to 1. It is an instruction that writes to the
same address. Accesses to the cache area are handled in the same way as ordinary data accesses.
8.4.5
When a cache miss occurs during a read, the data of the missed address is read from 1 line (16
bytes) of memory and replaced. It is therefore necessary to decide which of the four ways is to be
replaced. It can generally be expected that a way that has been infrequently used recently is also
unlikely to be used next. This algorithm for replacing ways is called the least recently used
replacement algorithm, or LRU. The hardware to implement it, however, is complex. For that
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EX: Instruction execution
MA: Memory access
WB: Write-back
Cache-Through Access
Pseudo-LRU and Cache Replacement
The TAS Instruction
pipeline stage
address bus
address bus
data bus
data bus
Figure 8.9 Reading Cache-Through Areas
Internal
Internal
Cache
Cache
CPU
I
EX
Address A
Address A
Address B
MA
EX
Address A
Address A
WB
MA