HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 445

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HD6417616

Manufacturer Part Number
HD6417616
Description
32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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10.1.3
The E-DMAC manages the transmit/receive buffers by means of corresponding transmit/receive
descriptor lists.
Transmission: The transmit E-DMAC fetches a transmit buffer address from the top of the
transmit descriptor list, and transfers the transmit data in the buffer to the transmit FIFO. If a
transmit directive follows in the descriptor, the E-DMAC reads the next descriptor and transfers
the data in the corresponding buffer to the transmit FIFO. In this way, continuous data
transmission can be carried out.
Reception: For each start of a receive DMA transfer, the receive E-DMAC fetches a receive
buffer address from the top of the receive descriptor list. When receive data is stored in the receive
FIFO, the E-DMAC transfers this data to the receive buffer. When reception of one frame is
finished, the E-DMAC performs a receive status write and fetches the receive buffer address from
the next descriptor. By repeating this sequence, consecutive frames can be received.
10.1.4
The E-DMAC has the seventeen 32-bit registers shown in table 10.1.
Notes: 1. All registers must be accessed as 32-bit units.
2. Reserved bits in a register should only be written with 0.
3. The value read from a reserved bit is not guaranteed.
Descriptor Management System
Register Configuration
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 2.00 Mar 09, 2006 page 419 of 906
REJ09B0292-0200

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