MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 30
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MC68HC912BD32CFU10
Manufacturer Part Number
MC68HC912BD32CFU10
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC68HC912BD32CFU10.pdf
(292 pages)
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Port Signals
Port A
Pinout and Signal Descriptions
MC68HC912BD32 Rev 1.0
SDO/MOSI
Pin Name
SDI/MISO
DIVBYP
CS/SS
SCK
RxD
TxD
Pin Number
Table 5 MC68HC912BD32 Signal Description Summary
68
67
66
65
62
61
70
The MC68HC912BD32 incorporates eight ports which are used to
control and access the various device subsystems. When not used for
these purposes, port pins may be used for general-purpose I/O. In
addition to the pins described below, each port consists of a data register
which can be read and written at any time, and, with the exception of port
AD, PE[1:0] and port SBI[1:0], a data direction register which controls
the direction of each pin. After reset all port pins are configured as input.
Port A pins are used for address and data in expanded modes. The port
data register is not in the address map during expanded and peripheral
mode operation. When it is in the map, port A can be read or written at
anytime.
Register DDRA determines whether each port A pin is an input or output.
DDRA is not in the address map during expanded and peripheral mode
operation. Setting a bit in DDRA makes the corresponding bit in port A
an output; clearing a bit in DDRA makes the corresponding bit in port A
an input. The default reset state of DDRA is all zeroes.
When the PUPA bit in the PUCR register is set, all port A input pins are
pulled-up internally by an active pull-up device. This bit has no effect if
the port is being used in expanded modes as the pull-ups are inactive.
Setting the RDPA bit in register RDRIV causes all port A outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
Freescale Semiconductor, Inc.
Slave select output for SPI master mode, input for slave mode or master mode.
Serial clock for SPI system.
Master out/slave in pin for serial peripheral interface
Master in/slave out pin for serial peripheral interface
SCI transmit pin
SCI receive pin
Clock divider bypass
For More Information On This Product,
Pinout and Signal Descriptions
Go to: www.freescale.com
Description
10-pins
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