MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 139

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MC68HC912BD32CFU10

Manufacturer Part Number
MC68HC912BD32CFU10
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
TFLG1 — Timer Interrupt Flag 1
9-timer
RESET:
Bit 7
C7F
0
C6F
6
0
C7F–C0F — Input Capture/Output Compare Channel “n” Flag.
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
TFLG1 indicates when interrupt conditions have occurred. To clear a
bit in the flag register, write a one to the bit.
Read anytime. Write used in the clearing mechanism (set bits cause
corresponding bits to be cleared). Writing a zero will not effect current
status of the bit.
When TFFCA bit in TSCR register is set, a read from an input capture
or a write into an output compare channel ($90–$9F) will cause the
corresponding channel flag CnF to be cleared.
Freescale Semiconductor, Inc.
For More Information On This Product,
C5F
5
0
Go to: www.freescale.com
Standard Timer Module
PR2
0
0
0
0
1
1
1
1
C4F
4
0
Table 27 Prescaler Selection
C3F
PR1
3
0
0
0
1
1
0
0
1
1
C2F
2
0
PR0
0
1
0
1
0
1
0
1
C1F
1
0
MC68HC912BD32 Rev 1.0
Reserved
Reserved
Prescale
Standard Timer Module
Factor
16
32
1
2
4
8
Bit 0
C0F
0
Timer Registers
$008E

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