MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 133

• Manufacturer Part Number: MC68HC912BD32CFU10
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

TIOS — Timer Input Capture/Output Compare Select
CFORC — Timer Compare Force Register
Timer Registers
3-timer
RESET:
RESET:
FOC7
IOS7
Bit 7
Bit 7
0
0
FOC6
IOS6
6
0
6
0
Input/output pins default to general-purpose I/O lines until an internal
function which uses that pin is specifically enabled. The timer overrides
the state of the DDR to force the I/O state of each associated port line
when an output compare using a port line is enabled. In these cases the
data direction bits will have no affect on these lines.
When a pin is assigned to output an on-chip peripheral function, writing
to this PORTTn bit does not affect the pin but the data is stored in an
internal latch such that if the pin becomes available for general-purpose
output the driven level will be the last value written to the PORTTn bit.
IOS[7:0] — Input Capture or Output Compare Channel Configuration
FOC[7:0] — Force Output Compare Action for Channel 7-0
Read or write anytime.
Read anytime but will always return $00 (1 state is transient). Write
anytime.
A write to this register with the corresponding data bit(s) set causes
the action which is programmed for output compare “n” to occur
immediately. The action taken is the same as if a successful
comparison had just taken place with the TCn register except the
interrupt flag does not get set.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = The corresponding channel acts as an input capture
1 = The corresponding channel acts as an output compare.
FOC5
IOS5
5
0
5
0
Go to: www.freescale.com
Standard Timer Module
FOC4
IOS4
4
0
4
0
FOC3
IOS3
3
0
3
0
FOC2
IOS2
2
0
2
0
FOC1
IOS1
1
0
1
0
MC68HC912BD32 Rev 1.0
Standard Timer Module
FOC0
IOS0
Bit 0
Bit 0
0
0
Timer Registers
$0080
$0081