MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 213

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MC68HC912BD32CFU10

Manufacturer Part Number
MC68HC912BD32CFU10
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Receive Interrupt
Enable Register
(RIER)
RIER
$xx08
43-sibus
H/S-RESET
W
R
RCVFIE
BIT 7
0
Figure 44 Receive Interrupt Enable Register (RIER)
The Receive Interrupt Enable Register allows to enable/disable the
different receive or SYNC pulse interrupt sources for different interrupt
requests. A hard or soft reset will clear the register.
RCVFIE — Receive FIFO Not Empty Interrupt Enable
RXIE — Receive Interrupt Enable
SYNAIE — Synchronization Pulse ALARM Interrupt Enable
SYNNIE — Synchronization Pulse NORMAL Interrupt Enable
SLMMIE — Slot Mismatch Interrupt Enable
XSYNIE — Xsync Pulse Interrupt Enable
BIT 6
RXIE
Freescale Semiconductor, Inc.
0
For More Information On This Product,
1 = A Receive FIFO not empty event will result in a receive FIFO
0 = No interrupt will be generated from this event.
1 = A receive event will result in a receive interrupt.
0 = No interrupt will be generated from this event.
1 = A SYNC pulse ALARM event will result in a SYNC pulse
0 = No interrupt will be generated from this event.
1 = A SYNC pulse NORMAL event will result in a SYNC pulse
0 = No interrupt will be generated from this event.
1 = A slot mismatch event will result in a general interrupt.
0 = No interrupt will be generated from this event.
1 = A SYNC pulse event will result in an XSYNC pulse interrupt.
0 = No interrupt will be generated from this event.
not empty interrupt.
interrupt.
interrupt.
SYNAIE
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BIT 5
0
Byteflight™ Module
SYNNIE
BIT 4
0
SLMMIE
BIT 3
0
BIT 2
0
0
MC68HC912BD32 Rev 1.0
XSYNIE
Programmer’s Model
BIT 1
Byteflight™ Module
0
BIT 0
0
0

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