MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 135

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MC68HC912BD32CFU10

Manufacturer Part Number
MC68HC912BD32CFU10
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
TSCR — Timer System Control Register
5-timer
RESET:
Bit 7
TEN
0
TSWAI
6
0
TEN — Timer Enable
TSWAI — Timer Stops While in Wait
TSBCK — Timer Stops While in Background Mode
TFFCA — Timer Fast Flag Clear All
Write has no meaning or effect in the normal mode; only writable in
special modes (SMODN = 0).
The period of the first count after a write to the TCNT registers may
be a different size because the write is not synchronized with the
prescaler clock.
Read or write anytime.
If for any reason the timer is not active, there is no 64 clock for the
pulse accumulator since the E 64 is generated by the timer prescaler.
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0 = Disables the timer, including the counter. Can be used for
1 = Allows the timer to function normally.
0 = Allows the timer to continue running during wait.
1 = Disables the timer when the MCU is in the wait mode. Timer
0 = Allows the timer to continue running while in background mode.
1 = Disables the timer whenever the MCU is in background mode.
0 = Allows the timer flag clearing to function normally.
1 = For TFLG1($8E), a read from an input capture or a write to the
TSBCK
5
0
reducing power consumption.
interrupts cannot be used to get the MCU out of wait.
This is useful for emulation.
output compare channel ($90–$9F) causes the corresponding
channel flag, CnF, to be cleared. For TFLG2 ($8F), any access
to the TCNT register ($84, $85) clears the TOF flag. Any
access to the PACNT register ($A2, $A3) clears the PAOVF
and PAIF flags in the PAFLG register ($A1). This has the
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Standard Timer Module
TFFCA
4
0
3
0
0
2
0
0
1
0
0
MC68HC912BD32 Rev 1.0
Standard Timer Module
Bit 0
0
0
Timer Registers
$0086

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