FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 69

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

Character time-out and RCVR FIFO trigger level interrupts have the same priority as the current received data
available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt.
FIFO Polled Mode Operation
With FCR bit 0 = “1” resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation.
Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation.
In this mode, the user’s program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO
Polled Mode are as follows:
There is no trigger level reached or time-out condition indicated in the FIFO Polled Mode, however, the RCVR and
XMIT FIFOs are still fully capable of holding characters.
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
SMSC DS – FDC37N769
1.
2.
1.
2.
3.
4.
5.
ADDR = 0
DLAB = 0
ADDR = 0
DLAB = 0
ADDR = 1
DLAB = 0
ADDR = 2
ADDR = 2
ADDR = 3
ADDR = 4
ADDR = 5
ADDR = 6
ADDR = 7
ADDR = 0
ADDR = 1
DLAB = 1
ADDRESS*
DLAB = 1
REGISTER
The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as
soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO
while servicing this interrupt) or the IIR is read.
The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time
whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time in
the transmit FIFO since the last THRE=1.
immediate, if it is enabled.
Bit 0=1 as long as there is one byte in the RCVR FIFO.
Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode, the IIR is not affected since EIR bit 2=0.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift register are empty.
Bit 7 indicates whether there are any errors in the RCVR FIFO.
Receive Buffer Register
(Read Only)
Transmitter Holding
Register (Write Only)
Interrupt Enable Register
Interrupt Ident. Register
(Read Only)
FIFO Control Register
(Write Only)
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register
Scratch Register (Note 4)
Divisor Latch (LS)
Divisor Latch (MS)
REGISTER NAME
Table 58 - Individual UART Channel Register Summary
DATASHEET
Page 69 of 137
REGISTER
SYMBOL
MCR
RBR
MSR
SCR
DLM
THR
FCR
LCR
DDL
LSR
IER
IIR
The transmitter interrupt after changing FCR0 will be
Data Bit 0
1)
Data Bit 0
Enable Received
Data Available
Interrupt (ERDAI)
”0” if Interrupt
Pending
FIFO Enable
Word Length
Select Bit 0
(WLS0)
Data Terminal
Ready (DTR)
Data Ready (DR)
Delta Clear to
Send (DCTS)
Bit 0
Bit 0
Bit 8
BIT 0
(Note
Data Bit 1
Data Bit 1
Enable Transmitter
Holding Register
Empty Interrupt
(ETHREI)
Interrupt ID Bit
RCVR FIFO Reset
Word Length
Select Bit 1
(WLS1)
Request to Send
(RTS)
Overrun Error (OE)
Delta Data Set
Ready (DDSR)
Bit 1
Bit 1
Bit 9
BIT 1
Rev. 02-16-07