FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 104

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

CR0B
CR0B can only be accessed in the configuration state and after the CSR has been initialized to 0BH. The default
value of this register after power up is 00H (Table 90). CR0B indicates the Drive Rate table used for each drive (see
Table 22). Refer to section CR1F on page 108 for the Drive Type register.
CR0C
CR0C can only be accessed in the configuration state and after the CSR has been initialized to 0CH. The default
value of this register after power up is 02H (Table 91). CR0C controls the operating mode of the UART. This register
is reset to the default state by a POR or a hardware reset.
SMSC DS – FDC37N769
DRT1
D7
FDD3
BIT NO.
3, 4, 5
0
1
2
6
7
DRT0
D6
UART 2 Duplex This bit is used to define the FULL/HALF DUPLEX
UART 2 MODE UART 2 Mode
UART 1 Speed This bit enables the high speed mode of UART 1.
UART 2 XMIT
UART 2 RCV
UART Speed
BIT NAME
DRT1
Polarity
Polarity
D5
DATASHEET
FDD2
DRT0
Table 90 - CR0B
Table 91 - CR0C
D4
0 = RX input active high (default).
1 = RX input active low.
0 = TX output active high.
1 = TX output active low (default).
operation of UART 2.
1 = Half duplex
0 = Full duplex (default)
5 4 3
0 0 0
0 0 1
0 1 0
0 1 1
1 x x
1 = High speed enabled
0 = Standard (default)
This bit enables the high speed mode of UART 2.
1 = High speed enabled
0 = Standard (default)
Page 104 of 137
Standard (default)
IrDA (HPSIR)
Amplitude Shift Keyed IR @ 500Khz
Reserved
Reserved
DRT1
D3
FDD1
DESCRIPTION
DRT0
D2
DRT1
D1
FDD0
DRT0
D0
Rev. 02-16-07