FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 101

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

CR05
CR05 can only be accessed in the configuration state and after the CSR has been initialized to 05H. The default
value after power up is 00H (Table 81).
Note
Note
SMSC DS – FDC37N769
1
2
:
:
NO.
BIT
Bits CR05[1:0] do not affect the Parallel Port FDC.
In the FDC37N769, the behavior of the DRVDEN1 Control CR03.4 depends upon the FDC Output Control
CR05.1 (Table 82). If the FDC Output Control is active DRVDEN1 will behave as described in the 669FR;
i.e., if CR03.4 is 0 the DRVDEN1 output pin assumes the value of the DRVDEN1 function, if CR03.4 is 1 the
DRVDEN1 output pin stays high. If the FDC Output Control is inactive the DRVDEN1 Control will have no
affect on the DRVDEN1 output pin.
1
4,3
0
2
5
6
7
1,2
1
FDC
Output
Type
Control
(R/W)
FDC
Output
Control
(R/W)
FDC
DMA
Mode
DenSel
Swap Drv
0,1
EXTx4
Reserved Read Only. A read returns 0.
NAME
BIT
0 = FDC Outputs are open drain (default).
1 = FDC Outputs are push-pull.
0 = FDC Outputs Active (default).
1 = FDC Outputs Tri-State.
0 = Burst mode is enabled for the FDC FIFO execution phase data transfers (default).
1 = Non-Burst mode enabled. The FDRQ and FIRQ pins are strobed once for each
byte transferred while the FIFO is enabled.
A high level on this bit, swaps drives and motor sel 0 and 1 of the FDC. A low level
on this bit does not (default).
Decoder (External 2-to-4 Decoder Required).
External 4 Drive Support: 0 = Internal 2 Drive Decoder (Default). 1 = External 4 Drive
Table 81 - CR05: Floppy Disk Setup Register
BIT 4
0
0
1
1
DATASHEET
Page 101 of 137
DESCRIPTION
BIT 3
0
1
0
1
DENSEL OUTPUT
Normal (default)
Reserved
1
0
Rev. 02-16-07