FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 111

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

CR29
CR29 can only be accessed in the configuration state and after the CSR has been initialized to 29H. The default
value of this register after power up is 00H (Table 111). CR29 controls the HPMODE bit and is used to select the IRQ
mapping (bits 0 - 3) for the IRQIN pin. Refer to IRQ encoding for CR27 (Table 109). Any unselected IRQ output
(registers CR27 - CR29) is in tristate.
CR2A
Register CR2A is reserved. The default value of this register after power up is 00H.
CR2B
CR2B can only be accessed in the configuration state and after the CSR has been initialized to 2BH. The default
value of this register after power up is 00H (Table 112). CR2B is used to set the SCE (FIR) base address ADR[10:3].
The SCE base address can be set to 224 locations on 8-byte boundaries from 100H - 7F8H.
set ADR10, ADR9 and ADR8 to zero.
SCE Address Decoding: nCS = ’0’ required to access SCE registers. A[2:0] are decoded as XXXb.
SMSC DS – FDC37N769
It is the responsibility of the software to ensure that two IRQ’s are not set to the same IRQ number.
Potential damage to chip may result. Note: Z = Don’t Care.
OUT2 bit
ADR10
UART1
DB7
BIT NO.
1
1
1
1
0-3
5-7
4
UART1
Output State
UART1 IRQ
de-asserted
de-asserted
ADR9
DB6
asserted
asserted
HPMODE
RESERVED
IRQIN
NAME
Table 112 - CR2B: SCE (FIR) Base Address Register
ADR8
DB5
OUT2 bit
UART2
DATASHEET
1
1
1
1
Selects the IRQ for IRQIN
See
Not Writeable, Reads Return “0”
0
1
UART2
ADR7
Table 111 - CR29
DB4
Output State
Page 111 of 137
UART2 IRQ
de-asserted
de-asserted
asserted
asserted
Select IRMODE (default)
Select IRR3
ADR6
DB3
DESCRIPTION
Share
IRQ
Yes
Yes
Yes
Yes
ADR5
DB2
Pin State
UART1
1
1
1
0
ADR4
IRQ PINS
DB1
Pin State
UART2
To disable the SCE,
Z
Z
Z
Z
ADR3
DB0
Rev. 02-16-07