FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 102

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

CR06
CR06 can only be accessed in the configuration state and after the CSR has been initialized to 06H. The default
value of this register after power up is FFH (Table 83). CR06 holds the floppy disk drive type IDs for up to four floppy
disk drives (see section Drive Type ID, Bits 4 - 5 on page 23).
CR07
CR07 can only be accessed in the configuration state and after the CSR has been initialized to 07H. The default
value of this register after power up is 00H (Table 84). CR07 controls auto power management and the floppy boot
drive.
SMSC DS – FDC37N769
FDC OUTPUT
BIT NO.
ID31
CONTROL
D7
0,1
(CR05.1)
2
3
4
5
6
7
0
0
1
FDD3
UART 2 Enable
UART 1 Enable
ID30
Table 84 - CR07: Auto Power Management and Boot Drive Select
Parallel Port
Floppy Boot
Floppy Disk
D6
BIT NAME
Reserved
Reserved
Enable
Enable
CONTROL
DRVDEN1
(CR03.4)
ID21
0
1
X
Table 83 - DR06: Drive Type ID Register
D5
This bit is used to define the boot floppy.
0 = Drive A (default)
1 = Drive B
Read as 0.
Read as 0.
This bit controls the AUTOPOWER DOWN feature of the Parallel Port.
The function is:
0 = Auto powerdown disabled (default)
1 = Auto powerdown enabled
This bit is reset to the default state by POR or a hardware reset.
This bit controls the AUTOPOWER DOWN feature of the UART2.
The function is:
0 = Auto powerdown disabled (default)
1 = Auto powerdown enabled
This bit is reset to the default state by POR or a hardware reset.
This bit controls the AUTOPOWER DOWN feature of the UART1.
The function is:
0 = Auto powerdown disabled (default)
1 = Auto powerdown enabled
This bit is reset to the default state by POR or a hardware reset.
This bit controls the AUTOPOWER DOWN feature of the Floppy Disk.
The function is:
0 = Auto powerdown disabled (default)
1 = Auto powerdown enabled
This bit is reset to the default state by POR or a hardware reset.
DATASHEET
FDD2
Table 82 - DRVDEN1 Control
ID20
TRISTATE
DRVDEN1
D4
(PIN 18)
Page 102 of 137
1/0
1
ID11
D3
NORMAL DRVDEN1 FUNCTION
DRVDEN1 FORCED HIGH
ALL FDD OUTPUT PINS ARE
TRISTATED
DESCRIPTION
FDD1
ID10
D2
DESCRIPTION
ID01
D1
FDD0
ID00
D0
Rev. 02-16-07