FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 29

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

Data Rate Select, Bits 0 - 1
These bits determine the data rate of the floppy controller. See Table 22 for the appropriate values.
No Precompensation, Bit 2
This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30
register mode. Unaffected by software reset.
RESERVED, Bits 3 - 7
Bits 3 to 7 are RESERVED. Reserved bits cannot be written and return 0 when read.
Status Register Encoding
During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the
command just executed.
.
SMSC DS – FDC37N769
NO.
NO.
BIT
BIT
7,6
1,0
5
4
3
2
7
6
5
4
3
2
1
IC
SE
EC
H
DS1,0
SYMBOL
EN
DE
OR
ND
NW
SYMBOL
Interrupt
Code
Seek End
Equipment
Check
Head
Address
Drive
Select
End of
Cylinder
Data Error
Overrun/
Underrun
No Data
Not
Writable
NAME
NAME
00 - Normal termination of command. The specified command was properly
executed and completed without error.
01 - Abnormal termination of command. Command execution was started,
but was not successfully completed.
10 - Invalid command. The requested command could not be executed.
11 - Abnormal termination caused by Polling.
The FDC completed a Seek, Relative Seek or Recalibrate command (used
during a Sense Interrupt Command).
The TRK0 pin failed to become a “1” after:
1. 80 step pulses in the Recalibrate command.
2. The Relative Seek command caused the FDC to step outward beyond
Unused. This bit is always “0”.
The current head address.
The current selected drive.
The FDC tried to access a sector beyond the final sector of the track (255D).
Will be set if TC is not issued after Read or Write Data command.
Unused. This bit is always “0”.
The FDC detected a CRC error in either the ID field or the data field of a
sector.
Becomes set if the FDC does not receive CPU or DMA service within the
required time interval, resulting in data overrun or underrun.
Unused. This bit is always “0”.
Any one of the following:
1. Read Data, Read Deleted Data command - the FDC did not find the
2. Read ID command - the FDC cannot read the ID field without an error.
3. Read A Track command - the FDC cannot find the proper sector
WP pin became a “1” while the FDC is executing a Write Data, Write Deleted
Data, or Format A Track command.
Track 0.
specified sector.
sequence.
DATASHEET
Table 31 - Status Register 0
Table 32 - Status Register 1
Page 29 of 137
DESCRIPTION
DESCRIPTION
Rev. 02-16-07