FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 103

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

CR08
CR08 can only be accessed in the configuration state and after the CSR has been initialized to 08H. The default
value of this register after power up is 00H (Table 85). CR08 contains the lower 4 bits (ADRA7:4) for the ADRx
address decoder. Bits D0 - D3 are Reserved. Reserved bits cannot be written and return 0 when read.
CR09
CR09 can only be accessed in the configuration state and after the CSR has been initialized to 09H. The default
value of this register after power up is 00H (Table 86). CR09 contains the upper 3 bits (ADRA10:8) of the ADRx
address decoder and the ADRx Configuration Control Bits D[7:6]. The ADRx Configuration Control Bits configure the
ADRx Address Decoder (Table 87).
CR0A
CR0A can only be accessed in the configuration state and after the CSR has been initialized to 0AH.
value of this register after power up is 00H (Table 88). CR0A defines the FIFO threshold for the ECP mode parallel
port. Bits D[5:4] are Reserved. Reserved Bits cannot be written and return 0 when read. Bits D[7:6] are the IR
OUTPUT MUX bits (Table 89) and are reset to the default state by a POR or a hardware reset.
Note:
The first two options were previously selected through CR04.
SMSC DS – FDC37N769
The function of the IR OUTPUT MUX bits and how they are reset has been modified from the FDC37C669.
ADRA7
CONFIGURATION
IR OUTPUT MUX
D7
D7
D7
Note: Upper Address Decode requirements: nCS = ’0’ is required to qualify the ADRx output.
(see Table 89)
D7
CONTROL
0
0
1
1
ADRx
ADRA6
Table 86 - CR09: ADRx Upper Address Decoder and Configuration
D6
D6
D6
D6
0
1
0
1
Table 85 - CR08: ADRx Lower Address Decode
CONFIGURATION
ADRA5
Active device to COM port (Default). That is, use pins IRRX and IRTX
(pins 88 and 89).
Active device to IR port. That is, use IRRX2, IRTX2 (pins 23, 24)
Reserved.
Outputs Inactive: IRTX and IRTX2 are High-Z.
D7
0
0
1
1
D5
D5
Table 89 - CR0A: IR OUTPUT MUX Bits
D5
CONTROL
Table 87 - ADRx Configuration Bits
RESERVED
ADRx
DATASHEET
Reserved
ADRA4
D6
0
1
0
1
Table 88 - CR0A
D4
D4
D4
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ADRx disabled
1 Byte decode
A[3:0]=0000b
8 Byte block decode
A[3:0]=0XXXb
16 byte block decode
A[3:0]=XXXXb
DESCRIPTION
D3
D3
THR3
D3
Mux Mode
ECP FIFO THRESHOLD
ADRA10
D2
D2
THR2
D2
Reserved
ADRA9
D1
D1
THR1
D1
ADRA8
THR0
D0
D0
D0
The default
Rev. 02-16-07