FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 89

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

Write Sequence of Operation
1.
2.
3.
4.
5.
6.
7.
EPP 1.7 Read
The timing for a read operation (data) is shown
in timing diagram EPP 1.7 Read Data cycle.
The host sets PDIR bit in the control
register to a logic "0".
nWRITE.
The host selects an EPP register, places
data on the SData bus and drives nIOW
active.
The chip places address or data on PData
bus.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus contains valid
information, and the WRITE signal is valid.
If
deasserted until the peripheral deasserts
nWAIT or a time-out occurs.
When the host deasserts nIOW the chip
deasserts nDATASTB or nADDRSTRB and
latches the data from the SData bus for the
PData bus.
Chip may modify nWRITE, PDIR and
nPDATA in preparation of the next cycle.
nWAIT
is
asserted,
IOCHRDY
This asserts
is
89
IOCHRDY is driven active low when nWAIT is
active low during the EPP cycle. This can be
used to extend the cycle time. The read cycle
can complete when nWAIT is inactive high.
Read Sequence of Operation
1.
2.
3.
4.
5.
6.
7.
8.
9.
The host sets PDIR bit in the control
register to a logic "1".
nWRITE and tri-states the PData bus.
The host selects an EPP register and drives
nIOR active.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus is tri-stated, PDIR
is set and the nWRITE signal is valid.
If
deasserted until the peripheral deasserts
nWAIT or a time-out occurs.
The Peripheral drives PData bus valid.
The Peripheral deasserts nWAIT, indicating
that PData is valid and the chip may begin
the termination phase of the cycle.
When the host deasserts nIOR the chip
deasserts nDATASTB or nADDRSTRB.
Peripheral tri-states the PData bus.
Chip may modify nWRITE, PDIR and
nPDATA in preparation of the next cycle.
nWAIT
is
asserted,
This deasserts
IOCHRDY
is