FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 175

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

Note:
Note:
NAME
NAME
NAME
CLOCKI
t1
t2
t1
t2
t3
t4
t5
t1
P C I _ C L K
n R E S E T _ D R V
Tolerance is
The RESET width is dependent upon the processor clock. The RESET must be active while
the clock is running and stable.
Clock Cycle Time for 14.318MHz (Note)
Clock High Time/Low Time for 14.318MHz
Clock Rise Time/Fall Time (not shown)
Period
High Time
Low Time
Rise Time
Fall Time
nRESET_DRV width (Note)
0.01%
FIGURE 9A - INPUT CLOCK TIMING
DESCRIPTION
DESCRIPTION
DESCRIPTION
FIGURE 9B – PCI CLOCK TIMING
FIGURE 9C - RESET TIMING
t 5
t 1
t1
175
t 1
t 3
t2
MIN
MIN
20
30
12
12
MIN
t 4
1.5
t 2
t2
69.84
TYP
TYP
TYP
35
MAX
MAX
MAX
33.3
5
3
3
UNITS
UNITS
UNITS
nsec
nsec
nsec
nsec
nsec
ns
ns
ns
s