FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 123

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

Status Register
This register is cleared on a reset. This register
is read-only for the Host and read/write by the
FDC37M81x CPU.
UD
C/D
IBF
UD
D7
Writable by FDC37M81x CPU. These
bits are user-definable.
(Command Data)-This bit specifies
whether the input data register contains
data or a command (0 = data, 1 =
command).
data/command write operation, this bit
is set to "1" if SA2 = 1 or reset to "0" if
SA2 = 0.
(Input Buffer Full)- This flag is set to 1
whenever the host system writes data
into the input data register. Setting this
flag activates the FDC37M81x CPU's
nIBF (MIRQ) interrupt if enabled. When
the FDC37M81x CPU reads the input
data
automatically reset and the interrupt is
cleared.
associated with this internal signal.
KCLK
KDAT
MCLK
MDAT
Host I/F Data Reg
Host I/F Status Reg
register
UD
D6
There is no output pin
DESCRIPTION
(DBB),
During
UD
D5
this
a
N/A: Not Applicable
bit
Table 50 - Resets
Table 49 - Status Register
UD
D4
host
is
123
HARDWARE RESET (RESET_DRV)
OBF
EXTERNAL CLOCK SIGNAL
The FDC37M81x Keyboard Controller clock
source is a 12 MHz clock generated from a
14.318 MHz clock. The reset pulse must last for
at least 24 16 MHz clock periods. The pulse-
width requirement applies to both internally (Vcc
POR) and externally generated reset signals. In
powerdown mode, the external clock signal is
not loaded by the chip.
DEFAULT RESET CONDITIONS
The FDC37M81x has one source of reset: an
external reset via the RESET_DRV pin. Refer to
Table 50 for the effect of each type of reset on
the internal registers.
C/D
D3
(Output Buffer Full) - This flag is set to
whenever the FDC37M81x CPU write
to the output data register (DBB).
When the host system reads the output
data register, this bit is automatically
reset.
Weak High
Weak High
Weak High
Weak High
00H
N/A
UD
D2
IBF
D1
OBF
D0