FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 14

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

SUPER I/O REGISTERS
The address map, shown below in Table 1,
shows the addresses of the different blocks of
the Super I/O immediately after power up. The
base addresses of the FDC, serial and parallel
ports can be moved via the configuration
registers. Some addresses are used to access
more than one register.
Note 1: Refer to the configuration register descriptions for setting the base address
Base+(0-5) and +(7)
Base+(0-7)
Base1+(0-7)
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
60, 64
ADDRESS
Table 1 - Super I/O Block Addresses
FUNCTIONAL DESCRIPTION
Floppy Disk
Serial Port Com 1
Serial Port Com 2
Parallel Port
SPP
EPP
ECP
ECP+EPP+SPP
KYBD
BLOCK NAME
14
HOST PROCESSOR INTERFACE
The host processor communicates with the
FDC37M81x through a series of read/write
registers. The port addresses for these registers
are shown in Table 1.
accomplished through programmed I/O or DMA
transfers. All registers are 8 bits wide. All host
interface output buffers are capable of sinking a
minimum of 12 mA.
LOGICAL
DEVICE
0
4
5
3
7
IrDA 1.0
NOTES
Register access is