FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 28

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

DIGITAL INPUT REGISTER (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT Mode
BIT 0 - 6 UNDEFINED
The data bus outputs D0 - 6 will remain in a
high impedance state during a read of this
register.
PS/2 Mode
BIT 0 nHIGH DENS
This bit is low whenever the 500 Kbps or 1 Mbps
data rates are selected, and high when 250
Kbps and 300 Kbps are selected.
BITS 1 - 2 DATA RATE SELECT
These bits control the data rate of the floppy
controller.
corresponding to the individual data rates. The
data rate select bits are
software reset, and are set to 250 Kbps after a
hardware reset.
RESET
COND.
RESET
COND.
See Table 11 for the settings
CHG
DSK
N/A
CHG
DSK
N/A
7
7
unaffected by
N/A
state
N/A
Tri-
6
1
6
N/A
state
N/A
Tri-
5
1
5
a
N/A
state
28
N/A
Tri-
4
1
4
BIT 7 DSKCHG
This bit monitors the pin of the same name and
reflects the opposite value seen on the disk
cable or the value programmed in the Force
Disk
Register LD8:CRC1[1:0]).
BITS 3 - 6 UNDEFINED
Always read as a logic "1"
BIT 7 DSKCHG
This bit monitors the pin of the same name and
reflects the opposite value seen on the disk
cable or the value programmed in the Force
Disk
Register LD8:CRC1[1:0]).
N/A
state
N/A
Tri-
3
1
3
Change
Change
DRATE
SEL1
N/A
state
N/A
Tri-
2
2
Register
Register
DRATE
SEL0
state
N/A
N/A
Tri-
1
1
(see
(see
nDENS
nHIGH
state
N/A
Tri-
0
1
0
Configuration
Configuration