FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 115

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

Stop Cycle Control
Once all IRQ/Data Frames have completed the
Host Controller will terminate SER_IRQ activity
by initiating a Stop Frame.
Controller can initiate the Stop Frame. A Stop
Frame is indicated when the SER_IRQ is low for
two or three clocks. If the Stop Frame’s low
time is two clocks then the next SER_IRQ
Cycle’s sampled mode is the Quiet mode; and
any SER_IRQ device may initiate a Start Frame
in the second clock or more after the rising edge
of the Stop Frame’s pulse. If the Stop Frame’s
low time is three clocks then the next SER_IRQ
Cycle’s sampled mode is the Continuos mode;
and only the Host Controller may initiate a Start
Frame in the second clock or more after the
rising edge of the Stop Frame’s pulse.
Latency
Latency
SER_IRQ bus in bridge-less systems with the
minimum Host supported IRQ/Data Frames of
seventeen, will range up to 96 clocks (3.84 S
with a 25MHz PCI Bus or 2.88uS with a 33MHz
PCI Bus). If one or more PCI to PCI Bridge is
added to a system, the latency for IRQ/Data
updates from the secondary or tertiary buses
will be a few clocks longer for synchronous
buses,
asynchronous buses.
EOI/ISR Read Latency
Any serialized IRQ scheme has a potential
implementation issue related to IRQ latency.
IRQ latency could cause an EOI or ISR Read to
precede an IRQ transition that it should have
and
for
IRQ/Data
approximately
updates
Only the Host
double
over
the
for
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followed. This could cause a system fault. The
host interrupt controller is responsible for
ensuring that these latency issues are mitigated.
The recommended solution is to delay EOIs and
ISR Reads to the interrupt controller by the
same amount as the SER_IRQ Cycle latency in
order to ensure that these events do not occur
out of order.
AC/DC Specification Issue
All SER_IRQ agents must drive / sample
SER_IRQ synchronously related to the rising
edge of PCI bus clock. SER_IRQ pin uses the
electrical specification of PCI bus.
parameters will follow PCI spec. section 4,
sustained tri-state.
Reset and Initialization
The SER_IRQ bus uses RESET_DRV as its
reset signal. The SER_IRQ pin is tri-stated by
all agents while RESET_DRV is active. With
reset, SER_IRQ Slaves are put into the
(continuous) IDLE mode. The Host Controller is
responsible for starting the initial SER_IRQ
Cycle to collect system’s IRQ/Data default
values. The system then follows with the
Continuous/Quiet mode protocol (Stop Frame
pulse width) for subsequent SER_IRQ Cycles. It
is Host Controller’s responsibility to provide the
default values to 8259’s and other system logic
before the first SER_IRQ Cycle is performed.
For SER_IRQ system suspend, insertion, or
removal application, the Host controller should
be programmed into Continuous (IDLE) mode
first. This is to guarantee SER_IRQ bus is in
IDLE state before the system configuration
changes.
Electrical