FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 142

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

Note 1: To allow the selection of the configuration address to a user defined location, these
Configuration Address Bytes are used. There is no restriction on the address chosen, except that A0
is 0, that is, the address must be on an even byte boundary. As soon as both bytes are changed, the
configuration space is moved to the specified location with no delay (Note: Write byte 0, then byte 1;
writing CR27 changes the base address).
The configuration address is only reset to its default address upon a Hard Reset or Vcc POR.
Note: The default configuration address is either 3F0 or 370, as specified by the SYSOPT pin.
TEST 4
Default = 0x00, on
VCC POR and VTR
POR
TEST 5
Default = 0x00, on
VCC POR and
VTR POR
TEST 1
Default = 0x00, on
VCC POR and VTR
POR
TEST 2
Default = 0x00, on
VCC POR and VTR
POR
TEST 3
Default = 0x00, on
VCC POR and VTR
POR
REGISTER
0x2C R/W
ADDRESS
0x2B R/W
0x2D R/W
0x2E R/W
0x2F R/W
Table 53 - Chip Level Registers
Test Modes: Reserved for SMSC. Users should not
write to this register, may produce undesired
results.
Bit[7] Test Mode: Reserved for SMSC. Users
should not write to this bit, may produce undesired
results.
Bit[6] 8042 Reset:
1 = Put the 8042 into reset
0 = Take the 8042 out of reset
Bits[5:0] Test Mode: Reserved for SMSC. Users
should not write to this bit, may produce undesired
results.
Test Modes: Reserved for SMSC. Users should not
write to this register, may produce undesired
results.
Test Modes: Reserved for SMSC. Users should not
write to this register, may produce undesired
results.
Test Modes: Reserved for SMSC. Users should not
write to this register, may produce undesired
results.
142
DESCRIPTION
STATE
C
C
C
C
C