FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 30

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

CONFIGURATION CONTROL REGISTER (CCR)
Address 3F7 WRITE ONLY
PC/AT and PS/2 Modes
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy
controller.
values.
PS/2 Model 30 Mode
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy
controller.
values.
BIT 2 NO PRECOMPENSATION
This bit can be set by software, but it has no
functionality. It can be read by bit 2 of the DSR
when in Model 30 register mode. Unaffected by
software reset.
RESET
COND.
RESET
COND.
See Table 11 for the appropriate
See Table 11 for the appropriate
N/A
N/A
7
0
7
0
N/A
N/A
6
0
6
0
N/A
N/A
5
0
5
0
N/A
30
N/A
4
0
4
0
BIT 2 - 7 RESERVED
Should be set to a logical "0"
BIT 3 - 7 RESERVED
Should be set to a logical "0"
Table 12 shows the state of the DENSEL pin.
The DENSEL pin is set high after a hardware
reset and is unaffected by the DOR and the
DSR resets.
N/A
N/A
3
0
3
0
NOPREC DRATE
N/A
N/A
2
0
2
DRATE
SEL1
SEL1
1
1
1
1
DRATE
DRATE
SEL0
SEL0
0
0
0
0