TMC22191 CADEKA [Cadeka Microcircuits LLC.], TMC22191 Datasheet - Page 53

• Manufacturer Part Number: TMC22191
• Description: Digital Video Encoders/Layering Engine
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

PRODUCT SPECIFICATION
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall system
performance is strongly influenced by the board layout.
Capacitive coupling from digital to analog circuits may
result in poor picture quality. Consider the following sugges-
tions when doing the layout:
• Keep analog traces (COMP, V
• The power plane for the TMC22x91 should be separate
• The ground plane should be solid, not cross-hatched.
• Decoupling capacitors should be applied liberally to V
• The PXCK should be handled carefully. Jitter and noise
far from all digital signals as possible.
from that which supplies other digital circuitry. A single
power plane should be used for all of the V
power supply for the TMC22x91 is the same for the
system’s digital circuitry, power to the TMC22x91 should
be filtered with ferrite beads and 0.1 F capacitors to
reduce noise.
Connections to the ground plane should be very short.
pins. For best results, use 0.1 F capacitor in
parallel with 47 F capacitors. Lead lengths should be
minimized. Ceramic chip capacitors are the best choice.
on this clock or its ground reference will translate to noise
on the video outputs. Terminate the clock line carefully to
eliminate overshoot and ringing.
GENLOCKING VIDEO DIGITIZER
TMC22071
REF
Figure 37. TMC22x91-to-TMC22071 Interface Circuit
, R
REF
) as short and as
DD
GHSYNC
CVBS 7-0
GVSYNC
pins. If the
PXCK
LDV
MICROPROCESSOR
DD
INTERFACE
8
Microprocessor I/O Operations
Various CLUT Read/Write operations are shown in Table 17.
Each step in the table requires a CS pulse (falling edge fol-
lowed by a rising edge) to execute.
For Write operations, R/W and A
and hold timing with respect to the falling edge of CS. D
must meet setup and hold timing with respect to the rising
edge of CS. These timing relationships are illustrated in Fig-
ure 10. When writing data into an internal register (i.e.
CLUT Address Register) an extra CS falling edge is required
to transfer the input data to that register. This requirement is
usually accomplished by executing the next step in the
sequence. If there is no planned next step in the sequence,
executing a Control Register Read step will meet the require-
ment and terminate the sequence.
For Read operations, R/W and A
and hold timing with respect to the falling edge of CS. Read
data on D
nated by the rising edge of CS as shown in Figure 11. When
reading Control Registers, valid data appears t
falling edge of CS. When reading CLUT locations, an extra
CLUT Read step is needed to set up the CLUT Read
sequence. This is accomplished in the table by executing an
extra CLUT Read step just before the CLUT Read sequence
which returns successive d, e, and f data. CLUT Read
sequences must be terminated an extra CS falling edge. This
requirement is usually accomplished by executing the next
I/O step. If there is no planned next step in the sequence,
executing a Control Register Read step will meet the require-
ment and terminate the sequence.
CVBS 7-0
GHSYNC
GVSYNC
PXCK
LDV
2
7-0
DIGITAL VIDEO ENCODER
8
is initiated by the falling edge of CS\ and termi-
TMC22x91
1-0
1-0
must conform to setup
27009A
must conform to setup
TMC22091/TMC22191
DOM
after the
7-0
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