TMC22191 CADEKA [Cadeka Microcircuits LLC.], TMC22191 Datasheet - Page 32

• Manufacturer Part Number: TMC22191
• Description: Digital Video Encoders/Layering Engine
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

TMC22091/TMC22191
VITS Insertion
In both NTSC and PAL, the TMC22x91 can be set up to
allow Vertical Interval Test Signals (VITS) in the vertical
interval in place of normal black burst lines (UBB). This is
controlled by Interface Control Register bit 7. If this bit is
LOW, UBB lines are black burst and are independent of
TMC22x91 input data. If the bit is HIGH, all vertical interval
UBB lines become UVV. UVV lines are active video and
depend upon data input to the TMC22x91. VITS lines may
carry special test signals or pass captioning data through the
encoder.
Edge Control
SMPTE 170M NTSC and Report 624 PAL video standards
call for specific rise and fall times on critical portions of the
video waveform. The TMC22x91 does this automatically.
The TMC22x91 digitally defines slopes compatible with
SMPTE 170M NTSC or CCIR Report 624 PAL on:
1.
2. Burst envelope.
3. Active video leading and trailing edges.
32
Table 12. Standard Timing Parameters
Notes:
1. XBP, VA, VC, and VB are 10-bit values. The 2 MSBs for these four variables are in Timing Register 18. See Table 3.
2. EH and SL are 9-bit values. A most significant "1" is forced by the TMC22x91 since EH and SL must range from 256 to 511.
3. Every calculated timing parameter has a minimum value of 5 except EH and SL which have minimum values of 256.
NTSC sqr.
CCIR-601
CCIR-601
CCIR-601
Standard
PAL-M 4x
NTSC 4x
PAL sqr.
sqr.pixel
PAL 15
PAL-M
PAL-M
NTSC
EH and SL may be extended to 767. Only the eight LSBs are stored in Timing Registers 1B and 1C.
Mpps
H and V Sync leading and trailing edges.
pixel
pixel
F
PAL
F
SC
SC
59.94 15.734266
59.94 15.734266
59.94 15.734266
50.00 15.625000
50.00 15.625000
50.00 15.625000
60.00 15.750000
60.00 15,750000
60.00 15,750000
Field
Rate
(Hz)
Horizontal
Freq.
(kHz)
(Mpps)
12.27
13.50
14.32
14.75
13.50
15.00
12.50
13.50
14.30
Pixel
Rate
PXCK
(MHz)
24.54
27.00
28.64
29.50
27.00
30.00
25.01
27.00
28.60
Freq.
SY
3A
3E
10
40
43
45
40
46
44
47
BR
0D
0C
0D
0B
0C
0D
11
07
08
09
BU
1F
1E
1C
1E
12
22
24
21
22
20
CBP
13
0F
13
12
21
22
21
13
13
15
Subcarrier Programming
The color subcarrier is produced by an internal 32-bit digital
frequency synthesizer which is completely programmable in
frequency and phase. Separate registers are provided for phase
adjustment of the color burst and of the active video, permit-
ting external delay compensation and color adjustment.
In Master or Slave mode, the subcarrier is internally syn-
chronized to establish and maintain a specified relationship
between the falling edge of horizontal sync and color burst
phase (SCH). In NTSC and PAL, SCH synchronization is
performed every eight fields, on field 1 of the eight-field
sequence. Proper subcarrier phase is maintained through the
entire eight fields, including the 25 Hz offset in PAL
systems. See the description of 8FSUBR under Test Control
Register bit 1 for the subcarrier reset function.
In Genlock mode, the phase and relative frequency of the
incoming video are transmitted by the TMC22071 Genlock-
ing Video Digitizer over the CVBS bus at the beginning of
each line, which synchronize the digital subcarrier synthe-
sizer. When key control register bit BUKEN is HIGH and
digitized burst from the TMC22071 is passed through to the
reconstruction D/A converter, the reference subcarrier for the
chrominance modulator is still synthesized within the
encoder.
XBP
4D
3F
6D
4C
14
23
54
73
26
26
VA
CA
BE
8B
F7
E8
15
03
11
86
Bf
Timing Register (hex)
VC
1D
2B
0E
FE
16
05
30
31
12
22
VB
9D
BF
AC
B5
B7
8B
17
77
93
99
Note 1
18
65
65
65
75
65
75
61
65
65
FP
1A
1B
19
12
13
15
19
16
19
18
PRODUCT SPECIFICATION
EL
1A
1C
1F
1D
1F
21
23
20
23
21
EH
BD
1B
6A
8E
A6
B5
8E
A5
90
70
2
SL
1C
4C
6E
84
93
71
9A
53
6E
84
2
SH
1D
3A
3A
3F
43
45
3F
47
3F
42
CBL
5D
1E
52
59
5F
61
58
62
52
57