TMC22191 CADEKA [Cadeka Microcircuits LLC.], TMC22191 Datasheet - Page 4

• Manufacturer Part Number: TMC22191
• Description: Digital Video Encoders/Layering Engine
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

TMC22091/TMC22191
In Slave mode, VHSYNC, VVSYNC, and PDC (optional)
are inputs to the TMC22x91. These inputs determine when
new lines, frames, and active picture areas begin. The exter-
nal controlling circuitry needs to establish the correct timing
for these signals.
Horizontal and vertical synchronization signals are digitally
generated by the TMC22x91 with controlled rise and fall
times on all sync edges, the beginning and end of active
video, and the burst envelope. All elements of horizontal
sync timing are programmable, as are the frequency, phase,
and duration of color burst.
Video Input
The TMC22x91 accepts genlocked synchronization data and
digital composite video signals from the TMC22071 Gen-
locking Video Digitizer over the 8-bit CVBS bus. The
encoder synchronizes its digital subcarrier oscillator to the
video input from the TMC22071 with this data. The compos-
ite video data output from the TMC22071 is passed to the
internal video switch for keying with the encoded pixel data.
Chroma Modulator
A 32-bit digital subcarrier synthesizer feeds a quadrature
modulator, producing a digital chrominance signal. The rela-
tive phases of the burst and active video portions of the sub-
carrier can be individually adjusted to compensate for
external phase errors and to effect a hue control.
Interpolation Filters
Interpolation filters on the luminance and chrominance sig-
nals double the pixel rate in preparation for D/A conversion.
This band-limited process greatly simplifies the output filter-
ing required following the D/A converters and dramatically
reduces sin(x)/x distortion.
4
MODE
GBR444
RGB444
YC B C R 444
YC B C R 422
COLOR INDEX
RGB15
GBR15
*C
MSB
23
G
R
G
R
Y
Y
P
7
7
7
7
4
4
7
B
and C
Figure 1b. Pixel Data Format (TMC22191 when CLUTs are Bypassed)
G
R
Pixel
R
are loaded on alternate LDV cycles
G
R
Y
Y
G
R
0
0
P
G
R
Y
Y
16
0
0
0
0
0
C
C
B 7
G
P
15
G
B
B7
B7
7
7
4
4
G
B
Pixel
C
C
G
B
B *
G
B
B
0
0
An interpolation filter on the CVBS data similarly raises the
sample rate of the video signal, for mixing with the encoded
pixel data.
Composite Video Switch
The Composite Video Switch selects between the composite
video input (CVBS) and the composite encoded pixel data
on a pixel-by-pixel basis, under the control of a key function.
Keying may be managed by hardware or software. The hard-
ware key input (KEY pin) directly controls the video switch.
The encoder may be programmed to operate with a data key,
represented by three 8-bit registers that compare with the 24
input bits. They operate in all input modes and may be indi-
vidually enabled or disabled.
D/A Converters
The analog outputs of the TMC22x91 are the outputs of
three 10-bit D/A converters, operating at twice the pixel
clock rate. The outputs are capable of driving standard video
levels into a doubly-terminated 75 coaxial video cable
(37.5 total load). An internal voltage reference is provided
which can be used to provide reference current for the three
D/A converters. For accurate video levels, an external fixed
or variable voltage reference source is recommended. The
video signal levels from the TMC22x91 may be adjusted to
overcome the insertion loss of analog low-pass output filters.
The D/A converters on the TMC22x91 may be powered-
down via Control Register 0E bits 5 and 6. The
COMPOSITE D/A is controlled by bit 6 and the LUMA and
CHROMA D/A converters are controlled by bit 5.
C
C
G
B
P
8 7
B0
B0
0
0
0
C
B
R
R
B
C
P
R7
4
7
R7
7
4
7
R
B
Pixel
C
C
R
B
R *
R
R
B
0
0
24393A
LSB
C
C
R
B
P
R0
R0
0
0
0
0
Format Control Register
PRODUCT SPECIFICATION
MSB
01011000
01010000
0101X000
0101X001
0101X011
01010010
01011010
LSB