TMC22191 CADEKA [Cadeka Microcircuits LLC.], TMC22191 Datasheet - Page 37

• Manufacturer Part Number: TMC22191
• Description: Digital Video Encoders/Layering Engine
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

PRODUCT SPECIFICATION
Master Mode
In Master mode, initial timing is determined from the
RESET input, and subsequent cycles result from pro-
grammed values in the Timing Control Registers. The Hori-
zontal Sync output, VHSYNC, goes LOW 18 PXCK clock
cycles after the device is reset. The 50% point of the falling
edge of sync LOW on line 4 of field 1 (NTSC) or line 1 of
field 1 (PAL) occurs at the COMPOSITE and LUMA out-
puts 56 clocks after reset, or 38 clocks after VHSYNC. See
Figure 14, Master Mode Timing.
COMPOSITE
VHSYNC
OUTPUT
RESET
PXCK
0
(GHSYNC)
1
VHSYNC
PXCK
PCK
KEY
LDV
2
PD
Figure 13. Slave Mode PD Port Interface Timing (Genlock Mode)
3
4
t SP
16
Figure 14. Master Mode Timing
2N+1
t PWHPX
17
t SP
t XL
18
t PWHLDV
t PWLVH
19
t HP
t PWLPX
20
Slave Mode
In Slave mode, the 50% point of the falling edge of sync
occurs 46 PXCK clocks after the falling edge of VHSYNC,
which is an input signal to the TMC22x91. This must be pro-
vided by the host to begin every line. If it is early, the line
will be started early, maintaining the 52 clock delay to out-
put. If it comes late, the front porch portion of the output
waveform will be extended as necessary. See Figure 15,
Slave Mode Timing.
21
2N+2
51
52
50% Sync Amplitude
53
54
t PWLLDV
2N+3
55
56
24340A
TMC22091/TMC22191
57
58
59
24353A
60
37