TMC22191 CADEKA [Cadeka Microcircuits LLC.], TMC22191 Datasheet - Page 13

• Manufacturer Part Number: TMC22191
• Description: Digital Video Encoders/Layering Engine
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

PRODUCT SPECIFICATION
Control Register Definitions
Global Control Register (00)
Reg
00
00
00
00
00
00
7
Bit
7-5
4
3
2
1
0
Reserved
Name
SRESET
PAL
LUMDIS
CHRDIS
HRESET
6
Function
Reserved.
Software reset. When LOW, resets and holds internal state machines and
disables outputs. When HIGH (normal), starts and runs state machines and
enables outputs.
Video standard select. When LOW, the NTSC standard is generated with 7.5
IRE pedestal. When HIGH, PAL standard video is generated. This bit is ignored
if Register 0E bit 7 is HIGH, enabling the 0E and 0F registers.
Luminance input disable. When LOW (normal), luminance (Y) data from
external frame buffer is enabled. When HIGH, luminance (Y) data into the
TMC22x91 is forced to 0 IRE but sync pulses continue from the LUMA output.
Chrominance input disable. When LOW (normal), burst and frame buffer data
into the TMC22x91 are enabled. when HIGH, burst and frame buffer data are
suppressed, enabling monochrome operation.
Software reset enable. SRESET is forced LOW when the RESET pin is taken
LOW. State machines are reset and held. When HRESET is LOW, RESET may
be taken HIGH at any time. The TMC22x91 is enabled and a new frame is
begun with line 1, field 1 on the next PXCK after SRESET is set HIGH. The D/A
converters are powered down while RESET is LOW. When HRESET is HIGH,
a new frame is begun with line 1, field 1 on the next PXCK after RESET is taken
HIGH. SRESET is ignored. The D/A converters remain active during the reset
sequence.
5
SRESET
4
PAL
3
LUMDIS
2
CHRDIS
1
TMC22091/TMC22191
HRESET
0
13