TMC22191 CADEKA [Cadeka Microcircuits LLC.], TMC22191 Datasheet - Page 35

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TMC22191

Manufacturer Part Number
TMC22191
Description
Digital Video Encoders/Layering Engine
Manufacturer
CADEKA [Cadeka Microcircuits LLC.]
Datasheet
PRODUCT SPECIFICATION
Figure 7. Modulated Ramp Waveform
D 7 -D 0
D 7 -D 0
A 1 -A 0
A 1 -A 0
R/W
R/W
CS
CS
t SA
t SA
Figure 10. Microprocessor Port – Write Timing
Figure 11. Microprocessor Port – Read Timing
t DOZ
t PWLCS
t PWLCS
t DOM
t HA
t HA
t SD
24388A
t PWHCS
t PWHCS
t HD
t HOM
Microprocessor Interface
The microprocessor interface comprises 13-lines. Two
address bits provide four addresses for device programming
and CLUT/register management. Address bit 0 selects
between control registers and CLUT memory. Address bit 1
selects between reading/writing the register addresses and
reading/writing register or CLUT data.
When writing, the address is presented along with a LOW on
the R/W pin during the falling edge of CS. Eight bits of data
are presented on D
CS.
One additional falling edge of CS is needed to move input
data to the assigned working registers.
7-0
during the subsequent rising edge of
24323A
24324A
TMC22091/TMC22191
35

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