TMC22191 CADEKA [Cadeka Microcircuits LLC.], TMC22191 Datasheet - Page 36

• Manufacturer Part Number: TMC22191
• Description: Digital Video Encoders/Layering Engine
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

TMC22091/TMC22191
In read mode, the address is accompanied by a HIGH on the
R/W pin during a falling edge of CS. The data output pins go
to a low-impedance state t
present on D
this port operates asynchronously with the pixel timing,
there is an uncertainty in this data valid output delay of one
PXCK period. This uncertainty does not apply to t
The RESET pin restores the TMC22x91 to field 1 line 1 and
places the encoder in a power-down state (if HRESET is
LOW). Bit 4 of the Global Control Register (SRESET) is set
LOW. All other control words and CLUT contents are left
unchanged. Returning RESET HIGH synchronizes the inter-
nal clock with PXCK and restores the device outputs to
active states.
Reading Pixel Data from the D
The microprocessor port of the TMC22x91 may be used to
monitor digital video outputs. The eight MSBs of the up-
sampled and interpolated pixel data that go to the
COMPOSITE D/A converter can also be accessed via the
D
and the Control Register pointer is loaded with 40
port will output the 8-bit composite pixels synchronous with
PXCK. To halt the pixel flow from D
HIGH.
Luminance pixel data may also be read from D
case, the eight MSBs of luminance at the input of the Sync
Reset Timing
The TMC22x91 operates from a master clock (PXCK) at
twice the pixel rate. In Master mode, the PCK to PXCK tim-
ing relationship is set on the rising edge of RESET. In Figure
12, PCK is denoted by odd PXCK counts.
When RESET is taken LOW with sufficient setup time (t
before a rising edge of PXCK, the internal state machines are
reset and the device is put into a mode as dictated by the Glo-
bal Control Register bits 0 and 4. In Master mode, when the
RESET pin is taken HIGH, the internal clock timing is estab-
lished. In Slave and Genlock mode, this timing is established
by VHSYNC and GHSYNC respectively. The first PXCK
following this RESET rising edge is designated as PXCK 1.
Where it is significant, reference PXCK timing will be
shown with numbered rising edges. A designation of 2N
clocks refers to an even number of PXCK rising edges from
device reset. If RESET is not shown and clock numbering
36
7-0
RESET
PXCK
port. When the Test Control Register is loaded with 28
7-0
t
DOM
after the falling edge of CS. Because
DOZ
ns after CS falls. Valid data is
t SR
7-0
Figure 12. Reset Timing – PCK Synchronization
7-0
, simply bring CS
Port
7-0
h
. In this
DOZ
, the D
.
SR
7-0
t HR
h
)
and Blank Insert block are monitored. When the Control
Register pointer is loaded with 60
8-bit luminance pixels synchronous with respect to PXCK.
To halt the pixel flow from D
Operational Timing
The TMC22x91 operates in three distinct modes:
1.
2. Slave mode. The encoder accepts horizontal and vertical
3.
does not refer to 2N, timing is relative to signals shown in
the diagram only.
Pixel Data Input Timing
PXCK is internally divided by 2 to generate an internal pixel
clock, PCK which is not accessible from the pins of the
TMC22x91. To ensure the correct phase relationship
between PCK and pixel data, PCK is locked to VHSYNC or
GHSYNC (Slave or Genlock mode, respectively). In Master
mode, VHSYNC is produced on the rising edge of PCK
allowing external circuitry to synchronize the generation of
pixel data and LDV which also operates at the rate of PCK.
The rising edge of LDV clocks the 24-bit pixel data into
three 8-bit registers while PCK clocks that data through the
pixel data path within the TMC22x91. It is therefore neces-
sary to meet the set-up and hold timing between pixel data
and LDV as well as LDV and PCK as shown in Figure 13.
Master mode. The encoder independently produces all
internal timing and provides digital sync to the host
controller.
sync from the controller and synchronizes the video out-
put accordingly.
Genlock mode. The encoder accepts horizontal and ver-
tical sync from the companion TMC22071 Genlocking
Video Digitizer, synchronizes itself to the incoming
video, and provides appropriate H Sync and V Sync to
the host. It synchronizes Pixel Data input in two ways:
a.
b.
1
t SR
Internal PDC. The encoder internally generates the
Pixel Data Control (PDC) signal which calls for
data input from the external pixel source.
External PDC. The encoder receives a PDC signal
from the host and accepts Pixel Data based on that
input.
2
7-0
, bring CS HIGH.
h
, the D
PRODUCT SPECIFICATION
7-0
port will output
3
24330A