TMC22191 CADEKA [Cadeka Microcircuits LLC.], TMC22191 Datasheet - Page 43

• Manufacturer Part Number: TMC22191
• Description: Digital Video Encoders/Layering Engine
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

PRODUCT SPECIFICATION
Hardware Keying
The KEY input switches the COMPOSITE D/A converter
input from the luminance and chrominance combiner output
to the CVBS data bus on a pixel-by-pixel basis. This is a
"soft" switch, executed over four PXCK periods to minimize
out-of-band spurious signals. The video signal from the
CVBS bus can only present on the COMPOSITE output. The
CHROMA and LUMA outputs continue to present encoded
PD port data when CVBS is active.
Hardware keying is enabled by the Key Control Register bit
6. Normally, keying is only effective during the Active Video
portion of the waveform as determined by the VA registers
15 and 18. The Horizontal Blanking interval is generated by
the encoder state machine even if the KEY signal is held
HIGH through Horizontal Blanking. However, it is possible
to allow digital Horizontal Blanking to be passed through
from the CVBS bus to the COMPOSITE output by setting
The key registers may be individually enabled using bits
3,2,1 of the Key Control Register. Bit 4 of the same register
enables/disables Data Keying in its entirety. Data Keying and
Hardware Keying are logically ORed: when both are
enabled, either one will result in a key switch to the CVBS
channel.
The key comparison is based on the input data to the tables
in the CLUT. When operating in color-index mode, all three
tables receive the same input value, so any one of the three
registers is sufficient to identify a key value. The outputs of
all enabled key registers are ANDed to produce the KEY sig-
nal. If more than one key register are enabled and their key
values are not identical, no key will be generated.
COMPOSITE
OUTPUT
PXCK
CVBS
KEY
PD
*
0
KEY is advanced five PXCK cycles when
Control Register OE bit 4 is HIGH (TMC22191).
V N+2
P N
1
*
2
V N+3
P N+1
3
4
V N+4
P N+2
5
6
V N+5
P N+3
7
Figure 22. Hardware Keying
8
V N+6
P N+4
9
Key Control Register bit 5 HIGH. In this mode, KEY is
always active, and may be exercised at will.
The KEY input is registered into the encoder just like Pixel
Data is clocked into the PD port. It may be considered a 25th
Pixel Data bit. It is internally pipelined, so the midpoint of
the key transition occurs at the output of the pixel that was
input at the same time as the KEY signal.
Data Keying
Data Keying internally generates a Key signal that acts
exactly as the external KEY signal. There are three Key
Value Registers 05, 06, and 07 that are matched against the
input data to the three tables in the CLUT. These tables are
designated D, E, and F. They contain different information
depending on the input mode selected as shown in Table 16.
Table 16. Table D, E, F Contents
V N+25
P N+23
38
YC
Mode
GBR
RGB
CI
B
39
C
R
V N+26
P N+24
40
41
Table D
Green
V N+27
P N+25
Red
CI
42
Y
43
V N+28
P N+26
KEY MIDPOINT
44
Table E
Green
Blue
45
C
CI
B
V N+29
P N+27
TMC22091/TMC22191
46
47
Table F
V N+30
P N+28
48
Blue
Red
C
CI
R
24359A
49
43