PIC18F2331 MICROCHIP [Microchip Technology], PIC18F2331 Datasheet - Page 38

• Manufacturer Part Number: PIC18F2331
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2331/2431/4331/4431
3.3.2
In SEC_IDLE mode, the CPU is disabled, but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered by setting the Idle bit,
modifying to SCS1:SCS0 = 01, and executing a SLEEP
instruction. When the clock source is switched (see
Figure 3-5) to the Timer1 oscillator, the primary oscilla-
tor is shut down, the OSTS bit is cleared and the
T1RUN bit is set.
FIGURE 3-5:
FIGURE 3-6:
DS39616B-page 36
T1OSI
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
Note:
CPU Clock
Note 1: T
Peripheral
PLL Clock
Program
Counter
Output
T1OSI
OSC1
Clock
Q1
SEC_IDLE MODE
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, a forced
NOP will be executed instead and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started; in such sit-
uations, initial oscillator operation is far
from stable and unpredictable operation
may result.
Q2
Wake from Interrupt Event
OST
PC
Q3
= 1024 T
PC
Q4
TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE
TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)
Q1
OSC
Q1
1
T
; T
OST
PLL
(1)
2
Q2
= 2 ms (approx). These intervals are not shown to scale.
PC + 2
3
OSTS bit Set
Clock Transition
T
Q3
PLL (1)
4
Preliminary
Q4
5
PC + 2
6
Q1
1
2
7
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After a 10 s
delay following the wake event, the CPU begins execut-
ing code, being clocked by the Timer1 oscillator. The
microcontroller operates in SEC_RUN mode until the
primary clock becomes ready. When the primary clock
becomes ready, a clock switch back to the primary clock
occurs (see Figure 3-6). When the clock switch is com-
plete, the T1RUN bit is cleared, the OSTS bit is set and
the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run.
Clock Transition
3
8
4
5
PC + 4
6
7
8
 2003 Microchip Technology Inc.
Q2
Q3 Q4
Q1
PC + 6
Q2
Q3