PIC18F2331 MICROCHIP [Microchip Technology], PIC18F2331 Datasheet - Page 285

• Manufacturer Part Number: PIC18F2331
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

22.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro
The user program memory is divided into five blocks.
One of these is a boot block of 512 bytes. The
remainder of the memory is divided into four blocks on
binary boundaries.
FIGURE 22-5:
TABLE 22-3:
 2003 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend:
Unimplemented
File Name
(PIC18FX331)
Program Verification and
Code Protection
®
Boot Block
devices.
8 Kbytes
Read 0’s
Shaded cells are unimplemented.
Block 0
Block 1
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
SUMMARY OF CODE PROTECTION REGISTERS
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2331/2431/4331/4431
WRTD
0000h
0FFFh
0200h
0FFFh
1000h
1FFFh
3FFFh
Bit 7
CPD
Address
—
—
—
—
Range
EBTRB
WRTB
Bit 6
CPB
—
—
—
PIC18F2331/2431/4331/4431
(PIC18FX431)
MEMORY SIZE/DEVICE
Boot Block
16 Kbytes
Block 0
Block 1
Block 2
Block 3
Preliminary
WRTC
Bit 5
—
—
—
—
—
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 22-5 shows the program memory organization
for 8- and 16-Kbyte devices, and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 22-3.
Bit 4
—
—
—
—
—
—
0000h
01FFh
0200h
0FFFh
1000h
1FFFh
2000h
2FFFh
3000h
3FFFh
Address
Range
EBTR3
WRT3
Bit 3
CP3
—
—
—
Block Code Protection
EBTR2
WRT2
Bit 2
CPB, WRTB, EBTRB
CP2
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
—
—
—
Controlled By:
EBTR1
WRT1
Bit 1
CP1
DS39616B-page 283
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—