PIC18F2331 MICROCHIP [Microchip Technology], PIC18F2331 Datasheet - Page 243

• Manufacturer Part Number: PIC18F2331
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

19.5
Synchronous Slave mode is entered by clearing bit
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the RC6/TX/CK/SS pin (instead
of being supplied internally in Master mode). This
allows the device to transfer or receive data while in
any low-power mode.
19.5.1
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 19-9:
 2003 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
BAUDCTL
SPBRGH
SPBRG
Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.
Name
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
If enable bit TXIE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
USART Synchronous Slave Mode
USART Transmit Register
Baud Rate Generator Register, High Byte
Baud Rate Generator Register, Low Byte
USART SYNCHRONOUS SLAVE
TRANSMIT
GIE/GIEH
SPEN
CSRC
Bit 7
—
—
—
—
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
PEIE/GIEL
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
TMR0IE
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
PIC18F2331/2431/4331/4431
INT0IE
CREN
SYNC
SCKP
Bit 4
TXIF
TXIE
TXIP
Preliminary
ADDEN
SENDB
BRG16
RBIE
Bit 3
—
—
—
TMR0IF
CCP1IE
CCP1IP
CCP1IF
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
BRGH
FERR
Bit 2
—
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
WUE
Bit 1
TMR1IF
TMR1IE
TMR1IP
ABDEN
RX9D
TX9D
RBIF
Bit 0
0000 000x
-000 -000
-000 -000
-000 -000
0000 -00x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
POR, BOR
Value on
DS39616B-page 241
0000 000u
-000 -000
-000 -000
-000 -000
0000 -00x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
Value on
all other
Resets