PIC18F2331 MICROCHIP [Microchip Technology], PIC18F2331 Datasheet - Page 216

• Manufacturer Part Number: PIC18F2331
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2331/2431/4331/4431
FIGURE 18-1:
DS39616B-page 214
RC4/SDI/SDA
RC5/SDO
RA5/SS/AN4
RC3/SCK/
SCL
Peripheral OE
Read
SS Control
Select
TRISC<3>
Edge
Enable
bit0
Select
Edge
SSPBUF reg
SSP BLOCK DIAGRAM
(SPI MODE)
SSPM3:SSPM0
SSPSR reg
Clock Select
4
2
Prescaler
Write
4, 16, 64
Clock
Shift
TMR2 Output
Data Bus
Internal
2
T
CY
Preliminary
To enable the serial port, SSP enable bit SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, reinitialize the SSPCON
register, and then set bit SSPEN. This configures the
SDI, SDO, SCK, and SS pins as serial port pins. For the
pins to behave as the serial port function, they must
have their data direction bits (in the TRISC register)
appropriately programmed. That is:
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set and ADCON must
.
cleared
be configured such that RA5 is a digital I/O
Note 1: When the SPI is in Slave mode with SS
2: If the SPI is used in Slave mode with
3: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
0100), the SPI module will reset if the SS
pin is set to V
CKE = 1, then the SS pin control must be
enabled.
pin control enabled (SSPCON<3:0> =
0100), the state of the SS pin can affect
the state read back from the TRISC<5>
bit. The Peripheral OE signal from the
SSP module into PORTC controls the
state that is read back from the
TRISC<5>
“PORTC, TRISC and LATC Registers”
for information on PORTC). If Read-
Modify-Write instructions, such as BSF,
are performed on the TRISC register
while the SS pin is high, this will cause the
TRISC<5> bit to be set, thus disabling the
SDO output.
 2003 Microchip Technology Inc.
DD
bit
.
(see
Section 10.3