PIC18F2331 MICROCHIP [Microchip Technology], PIC18F2331 Datasheet - Page 219

• Manufacturer Part Number: PIC18F2331
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

18.3
The SSP module in I
functions, except general call support, and provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the SCK/
SCL pin, which is the clock (SCL), and the SDI/SDA
pin, which is the data (SDA). The user must configure
these pins as inputs or outputs through the
TRISC<5:4> or TRISD<3:2> bits.
The SSP module functions are enabled by setting SSP
enable bit SSPEN (SSPCON<5>).
FIGURE 18-5:
The SSP module has five registers for I
These are the:
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) – Not directly
• SSP Address Register (SSPADD)
 2003 Microchip Technology Inc.
SCK/SCL
SDA
SDI/
accessible
Note 1: When SSPMX = 1 in CONFIG3H:
(1)
module
SSP I
(1)
SCK/SCL is multiplexed to pin RC5,
SDA/SDI is multiplexed to pin RC4, and
SDO is multiplexed to pin RC7.
When SSPMX = 0 in CONFIG3H:
SCK/SCL is multiplexed to pin RD3,
SDA/SDI is multiplexed to pin RD2, and
SDO is multiplexed to pin RD1.
Read
Clock
2
Shift
implements
C Operation
MSb
2
C mode, fully implements all slave
SSP BLOCK DIAGRAM
(I
Stop bit Detect
Match Detect
SSPADD reg
SSPBUF reg
2
SSPSR reg
Start and
C MODE)
the
LSb
standard
Write
(SSPSTAT reg)
Internal
Data Bus
2
Set, RESET
C operation.
S, P bits
Addr Match
PIC18F2331/2431/4331/4431
mode
Preliminary
The SSPCON register allows control of the I
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
• I
• I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC or TRISD bits. Pull-up
resistors must be provided externally to the SCL and
SDA pins for proper operation of the I
Additional information on SSP I
found in the PICmicro
Reference Manual (DS33023A).
18.3.1
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<5:4> or TRISD<3:2> set). The
SSP module will override the input state with the output
data when required (slave-transmitter).
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. They include (either
or both):
a)
b)
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 18-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow
condition. Flag bit BF is cleared by reading the
SSPBUF register, while bit SSPOV is cleared through
software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
SSP module, are shown in timing parameter #100 and
parameter #101.
2
C specification, as well as the requirements of the
Stop bit interrupts enabled to support Firmware
Master mode
Stop bit interrupts enabled to support Firmware
Master mode
port Firmware Master mode; Slave is Idle
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address), with Start and
C Slave mode (10-bit address), with Start and
C Start and Stop bit interrupts enabled to sup-
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
SLAVE MODE
2
C mode with the SSPEN bit set,
2
C modes to be selected:
®
Mid-Range MCU Family
2
C operation can be
DS39616B-page 217
2
C module.
2
C opera-