PIC18F2331 MICROCHIP [Microchip Technology], PIC18F2331 Datasheet - Page 180

• Manufacturer Part Number: PIC18F2331
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2331/2431/4331/4431
16.3
The Motion Feedback module includes three noise
rejection filters on CAP1/INDX, CAP2/QEA and
CAP3/QEB. The filter block also includes a fourth filter
for the T5CKI pin. They are intended to help reduce
spurious noise spikes which may cause the input sig-
nals to become corrupted at the inputs. The filter
ensures that the input signals are not permitted to
change until a stable value has been registered for
three consecutive sampling clock cycles.
The filters are controlled using the Digital Filter Control
(DFLTCON) register (see Register 16-3). The filters
can be individually enabled or disabled by setting or
clearing the corresponding FLTxEN bit in the
DFLTCON register. The sampling frequency, which
must be the same for all three noise filters, can be
REGISTER 16-3:
DS39616B-page 178
Noise Filters
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Unimplemented: Read as ‘0’
FLT4EN: Noise Filter Output Enable bit, T5CKI input
1 = Enabled
0 = Disabled
FLT3EN: Noise Filter Output Enable bit, CAP3/QEB input
1 = Enabled
0 = Disabled
FLT2EN: Noise Filter Output Enable bit, CAP2/QEA input
1 = Enabled
0 = Disabled
FLT1EN: Noise Filter Output Enable bit, CAP1/INDX input
1 = Enabled
0 = Disabled
FLTCK<2:0>: Noise Filter Clock Divider Ratio bits
111 =Unused
110 =1:128
101 =1:64
100 =1:32
011 =1:16
010 =1:4
001 =1:2
000 =1:1
bit 7
Legend:
R = Readable bit
-n = Value at POR
DFLTCON: DIGITAL FILTER CONTROL REGISTER
Note:
Note 1: Noise Filter Output Enables are functional in both QEI and IC operating modes
U-0
—
The Noise Filter is intended for random high-frequency filtering and not continuous
high-frequency filtering.
FLT4EN
R/W-0
FLT3EN
R/W-0
Preliminary
W = Writable bit
‘1’ = bit is set
FLT2EN
R/W-0
programmed by the FLTCK2:FLTCK0 configuration
bits. T
divider block.
The noise filters can either be added or removed from
the input capture or QEI signal path by setting or
clearing the appropriate FLTxEN bit, respectively. Each
capture channel provides for individual enable control
of the filter output. The FLT4EN bit enables or disabled
the noise filter available on TMR5CKI input in the
Timer5 module.
The filter network for all channels is disabled on POR
and BOR resets , as the DFLTCON register is cleared
on resets. The operation of the filter is shown in the
timing diagram in Figure 16-14.
CY
U = Unimplemented bit, read as ‘0’
‘0’ = bit is cleared
is used as the clock reference to the clock
FLT1EN
R/W-0
(1)
(1)
(1)
FLTCK2
R/W-0
 2003 Microchip Technology Inc.
x = bit is unknown
FLTCK1
R/W-0
FLTCK0
R/W-0
bit 0