PIC18F2331 MICROCHIP [Microchip Technology], PIC18F2331 Datasheet - Page 255

• Manufacturer Part Number: PIC18F2331
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

20.2
The A/D module has a 4-level result buffer with an
address range of 0 to 3, enabled by setting the FIFOEN
bit in the ADCON1 register. This buffer is implemented
in a circular fashion where the A/D result is stored in
one location and the address is incremented. If the
address is greater than 3, the pointer is wrapped back
around to 0. The result buffer has a buffer empty flag,
BEMT, indicating when any data is in the buffer. It also
has an overflow flag, BOVFL, which indicates when a
new sample has overwritten a location that was not
previously read.
Associated with the buffer is a pointer to the address for
the next read operation. The ADPNT<1:0> bits
configure the address for the next read operation.
These bits are read-only.
The Result Buffer also has a configurable interrupt
trigger level that is configured by the ADRS<1:0> bits.
The user has three selections: interrupt flag set on
every write to the buffer, interrupt on every second write
to the buffer, or interrupt on every fourth write to the
buffer. ADPNT<1:0> is reset to ‘00’ every time a
conversion sequence is started (either by setting the
GO/DONE bit, or on a trigger).
EQUATION 20-1:
EQUATION 20-2:
 2003 Microchip Technology Inc.
T
V
or
T
ACQ
Note:
C
HOLD
A/D Result Buffer
=
=
=
=
When right justified, reading ADRESL
increments ADPNT. When left justified,
reading ADRESH increments ADPNT.
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
T
(V
-(C
AMP
ACQUISITION TIME
MINIMUM A/D HOLDING CAPACITOR CHARGING TIME
REF
HOLD
+ T
– (V
)(R
C
REF
+ T
IC
+ R
/2048)) • (1 – e
COFF
SS
+ R
S
) ln(1/2048)
PIC18F2331/2431/4331/4431
(-Tc/C
Preliminary
HOLD
(R
IC
+ R
SS
20.3
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 20-2. The
source impedance (R
switch (R
required to charge the capacitor C
switch (R
(V
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 k . After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
To
Equation 20-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 20-1 shows the calculation of the minimum
required acquisition time T
converter module is fully powered up at the outset and
therefore the amplifier settling time, T
This calculation is based on the following application
system assumptions:
C
Rs
Conversion Error
V
Temperature
V
+ R
DD
HOLD
HOLD
DD
Note:
S
). The source impedance affects the offset voltage
))
calculate
)
A/D Acquisition Requirements
SS
SS
) impedance varies over the device voltage
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
) impedance directly affect the time
the
=
=
=
=
=
S
minimum
) and the internal sampling
9 pF
100
1/2 LSb
5V
50 C (system max.)
0V @ time = 0
ACQ
Rss = 6 k
HOLD
. In this case, the
HOLD
DS39616B-page 253
acquisition
) must be allowed
AMP
. The sampling
, is negligible.
time,